Cadence says 65nm users need CPR: new router to replace IC Craftsman

Cadence Design Systems Inc. is offering a replacement for its popular analog, AMS and full custom IC shape-based router, IC Craftsman, with what it believes to be a superior routing technology for design projects at 65nm and below.

The company's new Cadence Precision Router (CPR) is the second deliverable from Cadence's Catena advanced technology development group, a skunk works which Cadence formed in 2001 to develop advanced technology.

It's been a long time since Cadence has produced on its own a successful IC design tool, as the company has historically purchased tools and linked them together to create its flows. But Ted Vucurevich, Cadence's CTO, believes the new CPR running in concert with the company's Chip Optimizer, will prove to be a big hit and will replace IC Craftsman as the tool of choice for those folks routing the most complex analog, AMS and full custom digital ICs in 65nm silicon and lower.

Shape-based routers, like IC Craftsman, are traditionally more versatile than channel and grided routers, but have capacity and performance limits, and, as such, are not well suited to handling the large number of transistors afforded by 65nm and below.

CPR, said Vucurevich, doesn't have capacity problems, can route an entire MPU and can consider advanced silicon issues that would choke IC Craftsman.

"This is not a linear extrapolation of shape-based technology," said Vucurevich. '"We have the progenitors of shape based technology at Cadence and after looking at this space they had to come up with some new conclusions about what to do. I'm really excited about this approach because so far we have not seen anything that would limit the scalability of this solution through the useful life of CMOS."

CPR will be used in concert with Cadence's Chip Optimizer interconnect compiler tool which among other things performs via and wire optimization. Chip Optimizer, which Cadence introduced in January as the first deliverable of its Catena project, applies manufacturing rules to the physical model of the design. Vucurevich said Cadence introduced Chip Optimizer because designers using advanced processes had so many design rules to deal with and designers were struggling with determining the best manufacturing rule to use under a given condition.

"The tool's infrastructure has a sophisticated way of representing rules and then applying those rules when answering questions like where do need to put interconnect or where do I need to put space or where do I do a combination to do things like CMP optimization?" said Vucurevich. He said Chip Optimizer also uses electrical models to ensure that when a part of the design is routed, the operation is electrically valid.

The Chip Optimizer will serve interconnect and electrical rules data to CPR. Vucurevich said CPR is unique in that it is space-based router.

"It is a router where the drawn geometries are the basis from which it does all its operations,” said Vucurevich. "It has to maintain a connectivity model of these arbitrary geometries touching and connecting in arbitrary ways and it has to do it through the full 3D stack."

The Chip Optimizer and CPR flow has a "much smoother" refinement process than traditional router flows, said Vucurevich. "Traditional routers have a global route step then a detailed route step," he said. "The problem is the global step has to work very hard to predict what's going to happen in the detailed step. With new processes and more rules in manufacturing it gets harder for the global step to predict what detailed routing can and cannot do."

CPR still has a global step and a detailed step, but introduces an intermediate step primarily for long wire routes, typically the most critical routes, to ensure those traces are routed accurately.

"What it leads to is an incredibly incremental system," said Vucurevich. "We can use it to incrementally refine and once we have something use it to incrementally repair or modify. We found a way to increase the relationship between physical, connectivity and the manufacturing view without blowing up the data model." Vucurevich said one of the end results is that the tool produces 30 to 40% area savings over IC Craftsman.

The company counts IBM's processor group and ATI as CPR's first customers. Users will run the Chip Optimizer and CPR from Cadence's Virtuoso cockpit. The technology can also be used in Cadence's X-Architecture, which incorporates diagonal routing in addition to traditional north-south Manhattan grid routing.

Cadence isn't going to shelve IC Craftsman (which it gained in the mid-1990s when it acquired Cooper and Chyan Technology Inc.) and plans to improve it as technology for detailed block and cell level design above 65nm.

"At 65nm and below, Precision is what we will suggest users use," said Vucurevich.