"Sippy cups," power standards and completed features

Hey folks, wow, I've been working on back to back feature stories so I've been away from the blog for a while. The first of those back to back features should be in the 10/12 print edition of EDN and posted on our site that day, too. That one looks at three methodologies companies are employing in the age of global design. The second one, which I just finished is for our Global Design issue, which as far as I can tell runs in all versions of EDN (EDN North America, EDN Asia, EDN China…etc., simultaneously). This one covers the restrictions IP vendors place on their IP when doing business in emerging economies (India, Russia, and especially mainland China). I learned a bunch of new stuff in doing the interviews for the article. I hope you find it informative too. It will be in the 11/9 print edition of the many EDNs as well as posted online.

So now that I have my head out of the proverbial feature story sands, what's new folks? Any hot new developments in the EDA, ASIC or FPGA markets? Been getting a lot of emails urging me to attend Si2 and Accellera's efforts to merge two power standards into one. As I said in previous columns and posts I HATE covering standards. Let me know when they start so readers can have input and when they are completed so my readers can access them. The stuff that happens in between the start of the effort and the release of the effort is like listening to my kids fight over who gets the yellow sippy cup (For this Si2's Steve Schulz should be Sainted or at least be put on the shortlist for a Kaufmann award). I'll chime in on one thing regarding the power standards stuff, however.

Why isn't Apache involved in either the Cadence/Si2 backed effort or the Mentor/Accellera backed effort? And if they are now, why weren't they involved from the get go? I think you should at least have a market leading tool in the game to have clout as the originator of an industry standard. Last I looked Apache had all the marketshare in the power space and has been on TSMC's reference flow for years as THE provider of power integrity tools. Power wise, Cadence and Mentor have not. Andrew Yang (CEO of Apache), please give me your opinion on this? What's going on here? Is it just a cheesy play for your marketshare? Okay, maybe I'll stand for a little sippy cup argument, but just a little. Andrew, think of it as a live interview…