Global design & Actel's new sandman FPGA

Hey folks, sorry I haven't posted for a while but I've been working on (and just finished) a feature for the 10/12 issue of EDN. This particular piece examines three different global design team management styles. The three companies that make up the bulk of the article are Raza Microelectronics, Pixelworks and Open Silicon. It also has a sidebar looking at how NEC America and Infineon's ASIC Design and Security group deal with global design projects. Look for it in the Oct. 12^th issue, I hope you enjoy it and find it useful.

In the meantime however I recently spoke with the folks over at Actel about their new low power FPGA family called IGLOO.

The new IGLOO FPGA family is meant to serve as a sandman for a system. According to Martin Mason, director of silicon product marketing at Actel, the FPGA sits between the main processor and application chips and will power down other devices to conserve overall system battery life in wireless applications or perhaps simply save power in wired applications.

"Systems often need to bridge a processor to a mass storage solution, display technology or ASSP chips," said Martin Mason, director of silicon product marketing at Actel. "Those systems typically require an ASIC, CPLD or FPGA to be the bridge."

Mason notes that FPGAs tend to be the best choice for bridging because they are can be reprogrammed as application and system requirements change and they have higher capacities than CPLDs.

In the programmable arena, IGLOO is going up against specialty low power FPGAs like QuickLogic's one time programmable PolarPro and SRAM based CPLDs like Xilinx' CoolRunner and Altera's MAX families.

The new Actel device however is a 1.2V non-volatile, reprogrammable FPGA that can be powered down to run as low 5 microwatts static power.

Mason said users can program IGLOO to run in three low power modes: "Flash Freeze" mode aka slave mode, low active mode and sleep mode.

Flash Freeze mode is essentially a slave mode in which the power of the device is controlled by the processor. It takes 1 micro second for the processor to put the IGLOO in Flash Freeze mode and 1 micro second to take it out," said Mason. And when the device is put into Flash Freeze the power consumption drops to 5 microwatts. "What we do in Flash Freeze mode is make the device inert," said Mason. "The device remains powered on and the core contents (registers and SRAM) maintain states but we freeze the IO and the clocks inside the system. It's under control of processor in the system, which puts it into the lowest power mode."

He notes that while in Flash Freeze mode outputs become tri-state, while JTAG pins and phase locked loops do not consume power.

Low power active mode is IGLOO's master mode, which allows the device to control overall system power. "What we're doing here is essentially the same thing as Flash Freeze but keeping IOs active inside the system," said Mason. "In wireless applications this is used in things like keyboard scanners to see if someone is pushing a key on the phone to get some function to take place. When that happens it wakes up the system, runs the function and then puts the system back to sleep again."

The low power active mode is clocked with a 32-KHz clock and consumes about 25 microwatts.

IGLOO's sleep mode will power off devices. "It's very useful in very large devices," said Mason. "You can power down the device and get the power down to as low as 25 microwatts."

Actel will offer several IGLOO devices in its new family with densities ranging from 30,000 system gates to 3 million system gates.

The devices will be available in the fourth quarter of this year, running $1.50 at large volume. The company said users can prototype the devices today using its ProASIC3 devices.

Let me know if this sounds cool to you (Actel employees excluded, of course).