Will 4 competitors in IC P&R help or hurt users, the EDA and IC design landscape?

One of the more interesting aspects of the EDA landscape is the competition dynamic. Over the years I’ve noticed that a healthy amount of competition in any one tool niche is good in the EDA industry but too much competition tends to be bad for the industry and in the long run can be potentially bad for users too. From the mid-80s to the mid 90s, Synopsys Inc. downright owned the logic synthesis market. And for almost a decade had the market to themselves. They built a powerhouse, bought other companies and moved into other IC market segments on the strength of their Design Compiler tools, but after a while, their users started to complain at the lack of progress and some even called them arrogant. Then in the mid 1990s, Ambit popped up with its own synthesis tool. The Abmit BuildGates tool was serious enough to wake Synopsys up and indeed Synopsys started to respond by improving Design Compiler and for a few years held off Ambit from breaking into its marketshare too badly. The competition was good for users on many levels: Both companies were actively pushing to upgrade and improve their tools and users actually had a bit of leverage when dealing with one company or the other—they could simply say to one vendor, “sweeten the deal or I’ll go with your competitor” and get reasonable discounts on tools. But in desperate times, executives often make rash, short-sighted decisions that can actual hurt the overall market prospects for a tool segment. Shortly after Ray Bingham took over at Cadence, for one reason or another ((perhaps to meet short term earnings goals or simply to poison the well and or get a bit of revenge on Synopsys for entering the physical design space (traditionally Cadence’s strong suit)), Bingham’s management group decided to cut the price of Ambit’s synthesis tool to $25,000. Up until then, synthesis tools had been in the over $100,000 range. And once Cadence started offering Ambit at that price point, Synopsys also had to drop its prices. That was a great thing for users in the short term because they didn’t have to pay as much, but it also meant that it became a less lucrative EDA segment for both vendors, which in turn means less support and less R&D. Then when Magma and Get2Chip jumped into the logic synthesis space, it really diluted the segment so now lots of folks now believe logic synthesis, which is the tool segment that made the ASIC biz possible, is a commodity. So with this background in mind, I’m wondering how the digital IC implementation space will look going forward, now that all four of the largest EDA vendors are fielding tools for the segment. Is physical design different than synthesis? It’s interesting to note that when Cadence finally gained its first serious competitor in P&R with Avanti in the mid 1990sand then started to lose marketshare to Avanti in high-end ASIC designs, Avanti’s president and CEO, Gerald Hsu, actually raised the price of Avanti’s place and route system quarter after quarter. But that was when there were only two competitors. Over the last few years, we’ve seen three competitors in the space—Cadence, Synopsys (avanti), and Magma—and at the same time have heard reports that tighter competition has led to price erosion of place and route tools (though much of this overlapped with the economic recession and declining ASIC starts). Now that Mentor has acquired Sierra, I’m wondering what a fourth serious competitor means for the place and route space and for the EDA industry as a whole? I secretly hope that the greater competition means P&R vendors will churn out innovations more rapidly and EDA vendors with the best P&R will still get reasonable returns for their hard work. At the same time I sort of hope that the EDA vendors don’t start undercutting each other. In the short term that can be great for users and means they don’t have to spend a ton of money on top of increasing mask and other silicon related costs to get designs out the door—perhaps it means increases in design starts (very outside chance however). What it can also mean over the long run is that place and route may become a commodity and EDA vendors (and entrepreneurs building next gen P&R systems) will start to look for other tool segments for growth—thus the pace of innovations slows. Former Cadence CEO Joe Costello once likened the EDA industry to four dogs fighting over the same bowl of food. Today the bowl is larger, the amount of food is smaller, the dogs vary in size but now they all have the same amount of teeth. Let’s hope one with dulling teeth doesn’t lift its leg and aim for the bowl, otherwise you may be designing your sub-10 nm IC with an antiquated technology akin to a Spirograph, a sliderule and a roll of metalic tape.