Part 2 of Cooley survey shows SystemC use declinging; SystemVerilog increasing

Hey folks, John Cooley’s posted on deepchip.com Part 2 of his IC verification census, which features data indicating that SystemC use is decreasing while SystemVerilog use is increasing and that System Verilog assertion use is pulling away from the many contenders in assertion languages.

In part 2 of the survey, Cooley asks users "Do you see your project using SystemC in the next 6 months?" In the 2005 survey, 42% said yes, they do plan on using SystemC and 58% said no. Then for the 2007, survey Cooley asked "Is your project using SystemC? 23% said yes, while 77 said no.

“I have no idea what went wrong here,” Cooley writes in the study.“All I know is that the slick Synopsys Marketing weasils will say this just proves the ascendancy of their glorious System Verilog over a SystemC that they wisely abandoned years ago.Behind my back, the Cadence Marketing sleaze will attack me personally and call the

census ‘horribly biased’ and ‘that Cooley guy is not to be trusted.’"

In the 2007, Cooley also asked users to indicate what SystemC simulator they are using. The most popular, according to survey responses, is the OSCI free simulator, which 43% said they use. The most popular commercial simulator is Cadence’s NC-SystemC, with 33.6% of the votes, meanwhile Synopsys and Mentor tied for third greatest SystemC use, each getting 16% of the votes. It’s interesting to note that CoWare, who invented the language, only had 6.5% of the share, though it improved from 3.5% in the 2005 survey.

While the survey indicates SystemC use actually declined over the last two years, it indicates that System Verilog use doubled over the last two years.

While the data shows System Verilog use has gone up 2X in the past 2 years, precious few engineers are using SV for

actual chip design.The bulk are simulation and verification users. In the 2005 survey, Cooley asked users “Do you see your project using System Verilog in the next 6 months?” 19% said yes, while 81% said no. Then in the 2007 survey, Cooley asked, “Excluding assertions, is your project using System Verilog?” 35.1% said “yes,” while 64.9% said “no.”

The survey also used that the language is seeing its greatest use in verification/testbench. 80.2% said they use solely for verification, while 4.1% said they are using in only in design. 25.8% said they use it for both design and verification.

The most popular System Verilog tool appears to be Synopsys VCS though it appears to have lost some ground from 2005 to 2007, while Cadence has gained some ground.

In the 2005 survey, Cooley asked Whose System Verilog tools are you using? Synopsys VCS got 79% of the vote, to Mentor ModelSim’s 15% and Cadence’s 6%.

In the 2007, survey, Cooley asked “whose specific System Verilog tool(s) are you using? (Include everything from simulators to synthesis.)” Synopsys VCS gained the most votes with 65.6% followed by Cadence’s NC-Sim, with 24.7% then Mentor’s Questa, with 15% and Mentor’s ModelSim with 12.3%. Synopsys Design Compiler synthesis tool also gained 10.6% of the vote.

The 2007 survey also indicates that SystemVerilog as an assertion language is pulling away from the competition. System Verilog SVA got 37.8% of the votes while IBM Sugar/PSL got 14.9%, Synopsys Vera OVA got 9.6% and Verplex OVL/IAL got 9.3%.

The survey also indicates that tiny little Jasper Design Automation is gaining share in the “bug hunter’s tool” category.

The survey indicates that most verification groups don’t use bug hunter tools but of those that do 30.9% use Synopsys Magellan, 25.6% use Mentor 0-in, 24.2% use Cadence ISV/IFV/BlackTie. Meanwhile, 18.2% use Jasper, which is up from the 2005 survey, which indicated 10% of the bug hunter tool users were using Jasper.