EDA picking up, 45nm design challenges, Achilles and standards, and Brian Fuller’s new gig

Hi folks, is it me or has it seemed like a slow Summer for EDA news. There have been a few acquisitions but for the most part there haven’t been too many new product or new company announcements. I hope it means the EDA folks are quietly working hard to make the next 12 months a stellar year for product announcements. The summer news lull has been a bit of a blessing for me because it gave me quite a bit of time to work on my upcoming cover story on SoC design for 45nm. I spoke with all the big foundries, the folks from TI and Freescale and the top 4 EDA companies asking them essentially “What will designers need to know to design at 45nm that they didn’t need to know at 65nm?” The answers were very interesting but you’ll have to wait until the September 13 issue to see what they are.

There have been a few notable news items the last couple of days ( I have a feeling things are going certainly pick up) Yesterday, I spoke with the folks over at Cadence and Mentor about their collaboration on and intent to standardize on a new SystemVerilog verification methodology (“see Cadence and Mentor create free, open-source SystemVerilog methodology” ). The effort actually sounds very cool and is a big step toward, but not exactly, the type of collaboration I’ve been saying, and EDA users have been saying forever, should occur more frequently in the industry. In this case it is two companies, Mentor Graphics and Cadence, proposing essentially an industry standard against one company, Synopsys, that has the top marketshare in a given niche, but has a proprietary standard (though VMM isn’t a standard per se). The scenario of two companies with smaller share proposing a great standard going against a third with smaller share and a proprietary standard seems to be an age old them in EDA, much in the same way hubris has been a theme throughout the ages and from the beginning of the written word…starting with Homer’s account of the half-god Achilles in the Illiad. I can’t begin to recount all the times we’ve seen EDA companies fight over standards efforts. In my career, there’s been Verilog vs. VHDL, the Si2 vs .lib , CFI/Si2 Open access vs. Milkyway, CPF vs UPF, SKILL vs Python (pcells vs pycells), and probably a few others I don’t even know about.

There is one shining example of collaboration in the EDA industry: SPIRIT. I remember when I attended the SPIRIT announcement (I think it was at DATE in Paris many years ago). I remember the SPIRIT folks presenting the standards proposal and then naming off all the companies that were members/contributors. I was amazed because everyone was a member and everyone was collaborating…I think at one point I sort of teared up. At any rate, SPIRIT has turned into the golden example of how the EDA folks should work together.

As a final note, I’d like to congratulate my old mentor and friend, Brian Fuller, former editor in chief at EE Times, for landing a Vice President gig at PR firm Blanc & Otus. Congratulations, Brian…hope it didn’t hurt too much when the horns and the long, pointy tail came in…just kidding…