Between The Lines
EDN Senior Editor Mike Santarini covers digital design and the EDA, ASIC, and FPGA industries. [Editor's note: As of Feb. 2008, this blog is no longer active and is presented here for archival purposes.]
Wall Street and EDA: Radios for Christmas?
Hi folks, there’s interesting video interview on the street.com, in which Cadence CEO Mike Fister is being interviewed about the state of the semiconductor business. Big cheers to Cadence’s PR for setting up the spot. But the interview somewhat illustrates a sad truth: EDA still tends to be a bit too esoteric for the general business press. You’ll note that in this interview, ...... Read More
Comments (0)Karma for MPUs: is chip binning burning up?
A few weeks ago I attended a keynote at ICCAD in which, Jeff Welser, director of the SRC Nanoelectronics Research Initiative (NRI), outlined industry efforts to find a replacement for CMOS. Our coverage of that keynote is “CMOS running out of gas, new effort looks for scalable replacement, ICCAD keynoter says.” In his presentation, Welser whipped through a plethora of fascinating, ey ...... Read More
Comments (10)Deadline looming: EDA vendors get those EDN Innovation entries in ASAP
‘Tis the season for not only Eggnog, Santa Clause and Seasons greetings, here at EDN it’s time for nominations for our 2007 EDA Innovations of the year award, but the deadline is fast approaching. A few years back when I joined EDN, I started work after the selections for the 2004 Innovation award had already been submitted and the finalists selected (I had no say in who made the fin ...... Read More
Comments (0)A good read on aspect-oriented programming with the e testbench language
A months ago, I ran into blogger and verification specialist JL Gray and he gave me a copy of his business partner’s new book “Aspect-oriented programming with the e verification language—A pragmatic guide for testbench developers.” The author of the book and JL both work at Austin, TX-based design services company Verilab and over the years both have become devout user ...... Read More
Comments (1)The low cost FPGA battle between Xilinx, Altera, Lattice and Actel
Hi folks, we’ve posted my feature article on the low-cost FPGA market “High noon for FPGAs: Low-cost-versus- high-end showdown”, which I also discussed in a previous blog entry entitled “Is the FPGA industry cannibalizing itself?” You’ll note that the feature article focuses mainly on the business implications of low-cost FPGAs increasing functionality and ...... Read More
Comments (2)Intel, IBM & Sun's MPU groups want EDA IP, not tools
I went to the Open Access meeting today at the Sun Microsystems conference center and was pretty amazed how well the Silicon Integrated Initiative (Si2) and especially its Open Access (OA) effort are doing these days. The folks from Interoperable Pcell coalition repeated the demonstration from last week’s Synopsys Interoperability Forum showing several tools running IPL libraries via Open A ...... Read More
Comments (0)EDA-for-Brazilian-soccer-player exchange program and DAC in Rio de Janeiro? Sounds good to me.
I’m always amused when I read a report that one EDA vendor has landed a “primary tool provider agreement” with a given customer. Some of the more notable announcements along these lines are Cadence’s agreement with Freescale in 2005, Synopsys agreement with Intel earlier this year, and more recently Cadence’s agreement with the Brazilian government. (EETimes got ...... Read More
Comments (3)Apache's acquisition is Optimal
Don’t know if you’ve heard it yet but Apache announced it has acquired Optimal Corp. for an undisclosed amount. I’ve written about a lot of these EDA M&A deals over the years and this is one of the most promising acquitions, yet. Let’s face it, most EDA startups are launched with the express intent of getting purchased by a big vendor as soon as possible to get VCs ...... Read More
Comments (1)Upstart analog EDA PCell coalition IPL makes progress
Hi folks, just months after its founding, the Interoperable PCell Libraries (IPL) coalition is showing great progress, as this week at the Synopsys Interoperability developer’s forum the group demonstrated a multi-vendor analog/AMS tool flow running IPL’s newly released library on the Si2’s OpenAccess common database. In particular, IPL members demonstrated Silicon Navigator&# ...... Read More
Comments (10)Is the FPGA industry cannibalizing itself?
Hi folks, I just filed a feature on the low cost FPGA offerings from the various FPGA vendors, and I’m pretty happy with the article. The article focuses on how the low cost FPGA space is turning into the new battleground for FPGA vendors. Don’t know if you know this or not but Bryan Lewis over at research firm Gartner predicts that FPGA industry revenue will actually dip 1.9% in 200 ...... Read More
Comments (2)EDA M&A Scoop: Magma buys Rio Design for IC and package co-design
Magma Design Automation has acquired IC and package co-design tool vendor Rio Design Automation, EDN has learned. A company official at Magma confirmed that the company has indeed acquired Rio, but said Magma is not disclosing the terms of the agreement, as the acquisition price is considered an immaterial amount. The deal brings 10 new employees and a tool called RioMagic to Magma, which allows u ...... Read More
Comments (6)Even EDA ex-Avanti CEO Gerald Hsu has a blog
If you ever wondered what happened to Gerald Hsu after the infamous code theft trial between his company and Cadence Design Systems, you can find out on his blog post. Yep, even Gerry has a blog. I just happened to be searching the web and I noticed a blog post called Ratna’s Ergodic View. And in one post, there’s a mention that Gerry has a blog. Sure enough, he not only has a blog b ...... Read More
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