Intel and Micron's 3 Bit-Per-Cell MLC Flash: Even Lower-Cost Memory, Albeit With A Catch (Or A Few)

I was already impressed with the lithography and other technology achievements represented by IM Technologies’ 32 Gbit MLC NAND flash memories, which form the foundation of Intel’s second-generation solid-state drives. Imagine, then, how much more intrigued I was to learn that the company plans to evolve its silicon beyond today’s two-bit-per-cell approach to three-bits-per-cell by the end of this year. Translation: a near-identical piece of silicon to today’s ~16 billion storage transistor IC (albeit with tweaked charge sense circuitry, potentially leading to a marginally larger die size and fabrication cost) will soon be able to house 50% more information than before, 48 Gbits in total.

To understand how Intel and Micron achieved this objective, as well as the tradeoffs inherent to their accomplishment, let’s step back for a moment to flash memory fundamentals. Courtesy of Wikipedia, here’s a cross-section diagram of a flash memory cell:

NAND and NOR flash memory arrays predominantly differ in the cell access and related cell-to-cell interconnect schemes (which you can read about in more detail either at Wikipedia or in my book); the storage transistor fundamentals are largely the same. In its default fully erased state, a flash memory transistor’s turn-on characteristics are unaffected by the presence of the floating gate in-between the control gate and substrate. Programming a cell involves augmenting the floating gate with additional electron charge, typically via either channel hot-electron injection or reverse Fowler-Nordheim tunneling techniques in conjunction with the application of high voltage differentials.

Traditional one-bit per cell memories’ transistors exhibited only two states; fully erased and fully programmed, with only a several hundred electron floating gate storage difference between the two states at 34 nm, according to an unnamed Intel spokesperson earlier today. During a read attempt, the presence of current flow through the transistor, detected and amplified by a sense amplifier, was indicative of an ‘1′ erased state, while the absence of current (indicative of the floating gate’s added electrons’ prevention of transistor turn-on) coincided with a ‘0′ programmed state.

Flash forward (pun intended) to September 1997, when Intel introduced its first StrataFlash two-bit-per-cell device. Now, instead of two floating gate state levels per transistor, there were four, corresponding to the two resultant decoded bits per cell (11, 10, 01, or 00). Each state correlated to a far smaller differential allocation of electrons than in the simpler one-bit-per-cell past, which among other things necessitated more precise sense amplifier designs and consequent slower read speeds (to some degree counterbalanced by the fact that you were now simultaneously reading out two bits in parallel from each cell).

The programming (i.e. ‘write’) algorithm was also more complicated (translation: slower), since overshooting the desired number of electrons placed on the floating gate was an unacceptable scenario. Bulk erase, conversely, was largely unaffected since as before it returned all cells within the targeted block to a fully erased state, and since pre-programming all cells in a block to an all-0s state prior to erase (in order to avoid cell over-erase) had been in use since flash memory’s earliest days.

And what of reliability? Again, it was compromised in the two-bit-per-cell era. Cell disturbs (i.e. the unintended alteration of a given transistor’s floating gate electron allocation in either a positive or negative direction due to the read, write or erase of nearby transistors) were a bigger problem than before. Oxide degradation through repeated program/erase cycles also had a greater effect than in the one-bit-per-cell past. Grey code techniques, while boosting reliability, limited (for example) the ability to program the second bit of a two-bit cluster without needing to first fully erase the cell. And even in the absence of any stored data alteration, any variances in supply voltage and temperature had predictable degrading effects on the precision of the charge sense schemes.

Some applications, notably those with limited media write (and rewrite) requirements, with relaxed read and write performance expectations, with tight temperature and voltage tolerances, and/or which could encompass system-based EDAC to counterbalance media shortcomings, handled the two-bit-per-cell MLC hurdles with relative ease. Other applications have stayed with conventional one-bit-per-cell flash memory. And the same trends, albeit to a far more significant degree, will play out in the looming three-bit-per-cell era.

To wit, while I was unsuccessful in convincing Intel to more precisely quantify the earlier-mentioned ’several hundred electron’ estimate, a theoretical case study will hopefully still suffice to drive the point home. Say, for example, that ’several hundred electrons’ is 700. That means that at a threshold of 700 or more incremental electrons per floating gate beyond its default erased stasis condition, the chip outputs a ‘000′ pattern from the corresponding cell. On the other end of the spectrum, electron counts between 0 and 100 (minus state-to-state guard band) correspond to a ‘111′ fully erased pattern, and so on.

Factor in the added variables of voltage, temperature, and various cell disturb phenomena, and the magnitude of the challenge quickly becomes obvious…even more so if I’ve overestimated what ’several hundred electrons’ means! Comparative cost of one-, two- and three-bit-per-cell devices is more complicated than might appear to be the case at first glance. Die sizes, as earlier mentioned, are comparable since the raw number of storage cell transistors is the same. But encompass the incremental test time required to verify robust functionality of 2x or 3x the number of bits, along with the inevitable incremental yield loss especially at the early stages of a new technology’s life, and you shouldn’t expect a linear price decrease commensurate with a doubling or tripling of the amount of storage delivered by a given-sized chunk of silicon.

Intel and Micron aren’t the first to publicly claim mastery of three bits per cell, to be clear. Hynix started beating the drum last summer, although to the best of my knowledge, the company still hasn’t followed through on its initial October 2008 production schedule forecast. Sandisk and partner Toshiba similarly started talking about three (X3)- and four (X4)-bit-per-cell flash memory in mid-February…only time will tell if they execute on their nebulously worded second-half-2009 aspirations. Whenever three-bit-per-cell MLC flash memories arrive, regardless of who they come from, don’t expect to see them in highest-performance SSDs at least for a while. Cost-optimized SSDs are even a long shot, as are other big-ticket NAND applications such as digital still and video cameras, smartphones and portable multimedia players. But USB flash drives and throw-away consumer electronics widgets? Those are the platforms that’ll launch three-bit-per-cell flash memory’s inevitable success.

p.s…Regarding my month-back second-generation Intel SSD writeup, some of you may have heard that the company subsequently discovered an obscure bug in the initial production firmware. Apparently if you set a BIOS-based security password for the drive, then attempted to change or disable that password, the operation would leave the drive in a permanently inaccessible state. Well, as of Monday, you can consider that bug squashed…at least that’s what Intel’s sayin’…