Frontside Bus Follies

The first PowerMac G5 I purchased was a refurbished 1.6 GHz single-processor model that was dead on arrival. Its replacement had a nonfunctional front panel; the power LED and headphone jack (and maybe the Firewire and USB plugs, too, I didn't check) didn't work. To put it mildly, I was not enthralled.

After several colorful chats with various customer and technical support personnel, I was offered a 1.8 GHz model as a replacement. At first glance, it seemed to be reasonable compensation for my troubles. But then I read the fine print. Whereas the 1.6 GHz model's CPU had an 800 MHz FSB (frontside bus), the 1.8 GHz version's FSB was 600 MHz (I assume to maximize CPU yield and thereby minimize Apple's system cost). Any instructions that came out of the CPU's internal cache ran 200 MHz faster, but the bottleneck to the rest of the system was 200 MHz slower.

My gut feel was that the overall system performance of the 1.8 GHz model would be best-case on par with the 1.6 GHz predecessor, maybe even slower on some tasks, and a perusal of MacWorld's review confirmed my suspicion. Needless to say, I declined Apple's offer, and after a few more back-and-forths they proposed the dual-1.8 GHz variant (with 900 MHz FSB) that I now own. Fortunately I had the foresight to read the fine print, and the technical background to decipher it. Most consumers won't be so lucky.

This post was specifically prompted by today's unveiling of new PowerMac models. The single-CPU version again has a 3x FSB-to-core clock multiplier factor, while the more expensive dual-CPU variants employ more aggressive 2x multipliers. But it's not an IBM- and Motorola-only scenario. Intel's CPUs over time have adopted various combinations of FSB and core clocks; witness the 800 MHz and 1066 MHz Pentium 4 FSB variants in the company's current portfolio. AMD's processors have done, and do, the same thing, as do embedded processors and DSPs. It's all about balancing yield-and-cost versus performance, both from a CPU-centric standpoint and in a more systemic view that also encompasses the speed and cost of other subsystems such as memory, mass storage, network connectivity and the core logic inter-chip bus. Buyer beware.