ISSCC: Circuit Transformations Counterbalance Shrinking Transistors' Shortcomings
Judging from his two writeups posted earlier this (Monday) evening, both EDN's Ron Wilson and I were in attendance at this morning's third ISSCC keynote. The increasing transistor-to-transistor variation that ST Microelectronics' Joel Hartmann discussed is pretty mind-blowing; it's the result of shrinking transistor dimensions, therefore subsequent fewer dopant atoms in various transistor areas, and therefore a subsequent greater per-atom effect on each transistor's VT and other key parameters. As Intel's announcement (and IBM's near-coincident 'paper' announcement) of pending 45 nm production a bit over two weeks ago suggests, you'll sooner or later need to design your chips around the reality of this variability.
The issue wasn't restricted to this morning's keynote; it was also highlighted in several of the presentations at last (Sunday) night's special-topic session, 'Circuit Design In the Year 2012'. David Frank from IBM's PowerPC architecture team spoke on the 'Impact of Future Technology Scaling Options on Processor Design'; the good news is that chart after chart of simulation results showed that the performance-per-watt capability of the 32 nm process node was a much more significant improvement versus its 45 nm predecessor than the incremental improvement of prior 90-65 nm and 65-to-45 nm iterations. The bad news is that getting those results will require significantly more work than before; a notable percentage of Frank's material, for example, pragmatically focused on effectively removing generating heat from the die, versus the traditional full fixation on decreasing the amount of generated heat.
A follow-on Sunday presentation from Marcel Pelgrom of Philips Research, titled 'Digital Circuit Design Insights from Analog Experiences' echoed many of Franks' points as well as providing plenty of additional concerns and suggested resolutions. For logic circuits, the consistent theme both of yesterday's talks and this morning's was that traditional transistor dimensional scaling rates from one process generation to another just aren't sustainable any longer (Hartmann, early on in his talk, pointed out that it was theoretically possible to fit 16 iterations of a 32 nm-based chip design, in a 4×4 matrix, within a single 120 nm-based version of that same chip design; he then proceeded to decimate that theory). Internal voltages will need to remain higher than historical trends would otherwise suggest, and performance improvements will therefore need to come from other circuit innovations such as parallelization and pipelining. Pelgrom pointed out that reconfigurable logic could counterbalance malfunctioning logic blocks within the design, and he even suggested that a revival of differential logic might be in the cards.
What about SRAM? A glance at the multiple cache arrays that in sum total dominate the die area of a microprocessor, or those that fundamentally define the die area of a FPGA, suggests how important are the size, speed, and power consumption of SRAM circuits. Here too the transistor scaling of times past won't be sustainable; Frank suggested that engineers will need to instead focus on shrinking the space between devices. He also forecasted that embedded DRAM, as a SRAM alternative in less performance-critical usage models, would receive increased assessment as time progressed. Pelgrom indicated that 7, 8 or 10-transistor cells might become more popular in the future, as a means of insulating the circuit from transistor-to-transistor variability (thankfully, there'll be no shortage of cost-effective transistors at 45 and 32 nm process generations!). And Hartmann offered up optimized VDD and wordline voltages for each SRAM functional mode (read, write and retention) as a possible panacea.
