ISSCC: Sermons Focus on Foundries, MEMS

"'The growth rate of the semiconductor industry is beginning to slow down….Many of you are our customers. You are vitally important to us, and I think we are also vitally important to you". With these provocative words, TSMC's chairman Morris Chang launched into his 'Foundry Future: Challenges In the 21^st Century' leadoff keynote at this (Monday) morning's ISSCC plenary session. Early on in his talk, Chang shared some disturbing statistics with the audience; whereas from 1960 to 2000, yearly semiconductor industry growth averaged 16%, the projected average growth rate from 2000 to 2010 is only 6% (although from 2006 to 2010, the projected growth is a bit better albeit uncertainly so, at 9%).

Although the industry as a whole is underperforming this decade, certain segments are much healthier. Quantifying the captive fab-to-shared foundry shift that most semiconductor suppliers have either already executed or are in the process of implementing, Chang pointed out that over the years 1985 to 2005, foundries in general experienced an 18% average annual growth rate, with TSMC growing at an even faster 43% year-to-year rate. He then reminded the audience why this shift has occurred; for a chip vendor, a relationship with a foundry:

• Eliminates large capital expenditures for R&D and manufacturing
• Delivers optimized process technologies to meet specific cost and performance goals, and
• Provides flexibility for wafer capacity allocation

Whereas for the foundry, a broad scope of chip vendor partnerships opens the door to high volume cost (and other) learning advantages.

Chan offered up four strategies for future foundry-and-customer success. The first involves broadening beyond the CMOS-logic application, thereby adding other technology capabilities. The foundry penetration of the CMOS-logic market is currently above 70% (Chan believes it's nearing saturation). However, foundries have to date not penetrated other large IC markets to same extent; the estimated foundry percentage share of image sensors, analog, microprocessors and memory are all currently less than 20%. Embedded NVM, high voltage, CMOS image sensors, and color filters are all 'soon' to be added at TSMC, with other technologies necessary for portfolio-broadening (SiGe and embedded DRAM, for example) already available.

Strategy 2 involves managing circuit design complexity. Chan pointed out that design costs (not including mask costs) have recently been doubling for each process generation jump and will nearly triple from 90nm to 65nm. Key objectives necessary to fully executing this strategy include:

• Robust IP (both foundry-captive and third-party), design libraries, and EDA tools
• Providing early access to frequently used IP (such as USB and popular I/O standards)
• A comprehensive DFM design ecosystem, and
• Qualified design-service providers

TSMC's third strategy involves a deepening of the customer-foundry relationships. He pointed out that of the three main steps in this relationship:

• Process development (i.e. development of design guidelines for manufacturing)
• Product development (i.e. IC design) and
• Manufacturing ramp-up

only the second step has historically involved the customer, and in a near-exclusive fashion. Chang would like to see customers also participating in steps 1 and 3, and conversely he'd like to see TSMC engineers involved in customers' IC designs. However, he explicitly pointed out that secure firewalls, to protect each customer's proprietary information, were necessary for this vision to come to fruition.

Advantages of a more symbiotic relationship between foundry and customer through the entire process included:

• An increased incorporation of customer requirements into the foundry process technology
• Assurance of wafer capacity and cycle time goals
• Access to foundry design environments to reduce design time, and
• Vertically-integrated technology availability (design, wafer production, assembly, test), again for faster time-to-market

The final strategy mentioned by Chen was continued R&D and capital investment which, given a chart he showed plotting wafer shipments over time for various process technologies (with a dramatic process-to-process shipment increase, both at any particular point in process life and cumulative) is a critical prerequisite to continued semiconductor industry vitality. Chan closed with a bullish prediction; by 2010, he feels, 40% of all ICs will be foundry-fabricated.

The second plenary keynote 'Analog and Mixed-Signal Innovation: The Process-Circuit-System-Application Interaction', by Lewis Counts, an Analog Devices Fellow and VP of Technology, wasn't quite as sound bite-rich (or maybe this digital-specializing senior technical editor just didn't properly appreciate the material….though I did very much enjoy his introductory comment that digital logic's 1s and 0s were disappearing into an analog morasse of reduced voltage tolerances) but it closed with an intriguing teaser. Counts claimed that the five great long-standing analog design challenges are:

• Dynamic range
• Bandwidth
• The Absolutes: Volts, Amps, Seconds and Kelvins
• Power Efficiency, and
• Complexity

One of his case studies of how ADI is addressing those challenges was a software-defined radio with a MEMS-based front-end antenna selection block. And, when wrapping up his presentation, MEMS showed up again. Counts pointed out how the blossoming popularity of MEMS-derived accelerometers in consumer electronics applications (ADI makes the accelerometer in Nintendo's Wii game console's primary controller, for example). He then showed a die plot and in-operation video clip of a 1 square mm MEMS-based gyroscope with 7 micron 'flex' motion.

Followup: Here's Ron Wilson's thoughts on the ADI keynote. I'd recommend you also give his Practical Chip Design ISSCC coverage a perusal, especially if you're a transistor-level person. Given that my IC design background was dominantly digital and leveraged gate array and standard cell ASIC, as well as FPGA and PLD, foundations (not to mention the fact that the bulk of my engineering background is in system- versus IC-level design), Ron and I naturally bring different-but-symbiotic perspectives to a given topic.