ISSCC: Processor Plethora, Part Two
Continued from 'ISSCC: A Plethora of Processors'….
After the break, AMD formally unveiled its native quad-core Opteron processor, code-named Barcelona (appropriate, given that the in-progress 3GSM World Congress conference is taking place in that same city). The first implementation of AMD's K8L microarchitecture (also known as 'Revision H'), the chip offers a number of improvements over current K8-derived Athlon, Opteron and Turion CPUs aside from its 2-4x greater number of per-die cores; a 128-bit per-core FPU, for example, along with enhanced processing pipelines, HyperTransport 3.0 links and DDR3 memory support within the integrated Northbridge core. However, interestingly, the presenter chose to spend much of his time focusing on the chip's PLL and gated clock distribution network; a function, perhaps, of ISSCC's circuit-centric slant, combined with the conference's overall focus on performance-per-watt.
Built on a 65 nm low-k SOI process with 11 copper interconnect layers, Barcelona contains 463 million transistors and has a 283 mm2 die size. The presenter was only willing to commit to a "2 GHz and up" performance estimate along with noting that the chip operates at core voltages ranging from 0.8V to 1.4V, but the published paper provides more details, "In a 95W max power envelope, the target frequency is 2.2 to 2.8GHz at 1.15V." Each core contains separate 64 KByte two-way set associative caches for instruction and data, along with 512 KBytes of L2 unified cache. A core-shared 2 MByte L3 cache completes the on-chip memory picture.
Finally, the session's attention turned to the first fruits of startup P.A. Semi's labours; this is the company that the PowerPC faithful pointed to when Steve Jobs proclaimed nearly two years ago that due to PowerPC performance-per-watt shortcomings, Apple was switching to Intel CPUs. Targeting 25W peak (13W typical) power consumption, the company's PA6T-1682M contains dual 2 GHz 64-bit PowerPC cores, each with 64 KByte instruction and data caches, and sharing a 2 MByte L2. Each core also is mated to a companion 1066 MHz 64-bit DDR2 memory controller, and quoting the published paper, the chip also includes "a configurable I/O subsystem able to support two 10Gb and four 1Gb Ethernet MAC, eight PCI Express links of configurable width with an aggregate bandwidth of 6GBytes/s, and hardware acceleration for cryptography, XOR and network functionalities."
Not surprisingly, the PA6T-1682M implements some of the most extensive (and impressive) power management circuitry that I've seen so far at ISSCC. The presenter rattled off a laundry list of focus areas:
- System-wide optimization via microarchitecture
- Multiple VDD islands
- Adaptive voltage control
- Very fine grain clock gating, in the RTL from the very beginning
- A flop-based (versus latch-based) methodology
- A H-tree clock distribution scheme
- A multi-VT and long-Lgate design, to reduce leakage, and
- Separate power supplies for each core, for the SRAM arrays, and for the memory-and-I/O-controller subsystem
Two particularly notable power-related statistics stuck with me. In the paper, the company claims that the design contains 23,000 clock gating instances. The presenter further fleshed out this datapoint, claiming that the design averaged only 18 flipflops per clock gate. That's aggressive power management. The chip die size, implemented in eight-metal layer 65 nm CMOS, is 115mm2. However, the company revealed no transistor count numbers, and no performance specifications, thereby begging the unanswered question of how real the design is. Time will tell….
Followup: Here's some more chip data, from P.A. Semi, after they saw my writeup yesterday:
- Transistor count: 200M
- Transistor count per core: 21M
- Total memory bits: 24M
- Total flop counts: 468K
And, the company assures me, the chip is sampling and therefore very much real….
