Paul and the Three Ps
Intel likes to talk about its *Ts….the foundation technologies on which it's building its processor efforts going forward. For those of you insufficiently indoctrinated in the 'Intel Way', they include (my comments are in parentheses):
- (On-hiatus, if not extinct) Hyper-Threading Technology
- Vanderpool Technologies (now known as Intel Virtualization Technology)
- Intel® Extended Memory 64 Technology
- Intel® Active Management Technology, and
- LaGrande Technology (i.e. security features built into CPUs, core logic chipsets, etc)
For tonight's Day 1 IDF rundown, I'd instead like to focus on what I've coined Intel's '3 Ps'. For the first nearly-20 years of Intel's existence, the company was predominantly focused on products; microprocessors, their support chips, nonvolatile and volatile memories, etc. With Craig Barrett's ascendancy to the Vice President seat in the mid-1980s, coupled with the competitive threat from Japanese DRAM manufacturers, Intel's focus broadened to comprehend process, i.e. low-cost, high-volume, fast-ramping manufacturing of chips built on leading-edge lithographies, exemplified by Barrett's showcase Copy Exactly philosophy. And, of course, over the past few years the company's focus has once again broadened to encompass the third 'p', platforms, such as the Centrino brand for mobile computing, along with the follow-on Viiv for the home and vPro for business environments.
All three elements (but not any mention of Intel's recently announced massive layoffs) were present in CEO Paul Otellini's keynote this morning, to varying degrees. Absent any compelling near-term CPU news (aside from a dual-side-by-side-die. single-package, quad-core proliferation of the existing Conroe chip, due out sometime in November), and with no new platforms to unveil (only updates on already-revealed marketing monikers), process innovations took center stage. Otellini proudly pointed out that by next week, the company will have shipped its 40 millionth microprocessor based on 65 nm technology, versus zero claimed shipments-to-date from any other CPU manufacturer. As AnandTech rightly points out, only about 5 million of those CPUs are based on the Core 2 microarchitecture….prior-generation Pentium M and NetBurst-based processors still constitute the dominant share of Intel's near-term business, although this'll quickly flip.
This month also marks the threshold at which 65 nm-based processor shipments will begin exceeding the number of CPUs built on a 90 nm lithography. And of course, Intel's already hard at work on its follow-on 45 nm process, with 15 different microprocessor designs currently under development (including, Intel's Stephen Smith admitted in a follow-on press briefing, monolithic quad-core configurations). Production shipments of 45 nm-based products will begin in the 2nd half of next year, ramping first in Portland, OR-based development Fab D1D (the source of today's 45 nm test wafers), followed by Chandler, AZ Fab 32 and then Israel-based Fab 28. Each fab, when fully outfitted, will have cost Intel roughly $3 billion USD.
In the follow-on press and analyst briefing, I tried to pin down Smith for some specifics regarding the fact that all four cores of Intel's 'quad' chip (formerly code-named Kentsfield and now known as the price-TBA Core 2 Extreme QX6700, with the server-tuned spin still referred to as Clovertown), share a common front-side bus. As compared to AMD's architectural approach which links multiple cores (and CPUs containing those cores) through dedicated HyperTransport connections, Intel's single-bus scheme conceptually harbors the possibility of constrained performance due to FSB bottlenecks, especially with code that doesn't nicely fit within each core's L1-plus-L2 cache allocation. Intel's historical answer to this question had referenced the ever-faster FSB speeds over time….1066 MHz on modern desktop CPUs, and 1333 MHz on server-targeted Xeon chips. However, although the FSB is speedier than it has been in the past, four cores (not two) will soon be contending for it. Smith assured me that abundant benchmark data to be presented in coming-day technical sessions would reassure me; I'll report back if I'm not assuaged after perusing it.
