Moore's Law Matures....More
Continued from 'Moore's Law Matures'….
Even more significant, in my mind, is the power consumption-shrinking accomplishment that Nvidia pulled off. Both the GeForce 6800 Ultra and its GeForce FX 5800 and 5900 Ultra predecessors took up two add-in cards' worth of motherboard surface area, because of the huge fans Nvidia had to bolt on top of the chips in order to keep them cool (more than one 5800 reviewer drew an analogy between the 5800 fan's noise and the din of a vacuum cleaner), and required supplemental power supplies beyond what the AGP or PCI Express bus connector could deliver. The GeForce 7800 GTX, in comparison, is a single-slot design, with no supplemental power requirement. In this desktop PC-targeted graphics chip, Nvidia incorporated the full range of power management techniques (such as the "heavy use of clock gating") that it had already been employing in its mobile GPUs for several years.
For another example, consider Texas Instruments' recently introduced Aureus DA708 and DA710 audio DSPs (high-level vital statistics: both devices are currently sampling and are slated for volume production in the fourth quarter, the 250 MHz TMS320DA708 costs $13.52 in 10,000 unit quantities and comes in a 144-pin TQFP package, the 300 MHz TMS320DA710 costs $21.63 and comes in a 256-ball BGA package). According to the company, they're built on the exact same manufacturing process as their DA6xx precursors. Yet TI claims they deliver 50% more device performance (30% of it due to architectural enhancements, the rest due to clock speed boosts). How'd they pull off that hat trick?
After much arm-wrestling, I was able to yank the following tech nuggets out of TI's tight-lipped technical folks. The DA7xx DSPs contain a 32 Kbyte instruction-only cache, whereas 6xx chips incorporated separate 4 Kbyte instruction and data caches. The top-end clock speed on the DA610 was 250 MHz; the DA710 boosts that rate by 20%. Here's more, direct from the source: "TI developed several innovative optimizations which are code compatible with TI’s entire portfolio of C67x DSPs….Improvements include:
- Implementing a dMAX DMA engine to offload the processor for specialized off-chip memory accesses during effects processing.
- Providing new mixed precision instructions, including 32-bit by 32-bit multiplication with a 64-bit result and 32-bit by 64-bit multiplication with a 64-bit result, to improve high-quality FIR and IIR filter performance efficiency in high-sample rate, low-frequency audio applications.
- Including a flat-memory model for more deterministic application performance.
- Doubling the number of internal registers from 32 to 64 to improve performance in register-bound kernels, as well as making compiler optimizations easier.
- Doubling the number of concurrent floating-point add instructions from two to four to boost FFT processing by 20 percent.
Translation: more intelligent use of the transistors that the cost target budget allowed, in order to get more useful work out of each clock edge, versus a historical shrink-the-transistors-and-add-more-and-crank-up-the-clock strategy.
A more sophisticated approach to product development requires more work, both in the up-front architecture definition, in the design, and in the debug and validation….along with corresponding crafting of the process the chip is manufactured on, and of the software the chip will run. I'm already seeing that, for example, the historical every-six-month pace of significant new graphics chip announcements has dramatically slowed. But I much prefer analyzing the chips that come from the refined development process; you end up with a lot more giant-step revolutions, and a whole lot less baby-step evolutions. And I bet many of you prefer designing with them. Am I right?
