The Intel Developer Forum: 45 nm Now, Nehalem Next Year, 32 nm In Two

Continued from ‘The Intel Developer Forum: Tick, Tock, How Long-Running Is AMD’s Relevance Clock?‘…

To provide context for Intel’s predictions at this week’s show, a brief history lesson might be useful:

• Less than two years ago, Intel showcased its first functional 45 nm test wafer, whose die comprised SRAM arrays and various analog and digital logic circuits.
• One year later (this past January), Intel demonstrated first functional prototypes of its various 45 nm-based Penryn processor products; dual- and quad-core CPUs for both desktop and server PCs, along with a dual-core mobile CPU.

This week, Intel confirmed that its first Penryn products will be in full production in mid-November, and indicated that defect density improvement rates for the underlying 45 nm process were running ahead of historical trends for 130nm, 90nm and 65nm predecessors. Intel also revealed its first functional 32nm test circuit wafer. And (from Smith’s presentation)…

45 nm-based product shipments are anticipated to exceed those of today’s 65 nm-based products within a year

Penryn die are substantially smaller than their 65 nm precursors, even though they contain 50% more L2 cache

That added cache, along with additional multimedia-intended SSE instructions and other microarchitecture fine-tuning (explained in more detail here), delivers a tangible performance boost even at the same core and front side bus clock speeds (with product variants anticipated to spec upticks of both clock metrics).

Next-generation Nehalem microarchitecture-based CPUs and corresponding chipsets were demonstrated at both Paul Otellini and Dadi Perlmutter’s keynotes (the latter in full-blown laptop form), and will be in production within the year.

The above foil summarizes Nehalem’s key improvements over Penryn. I’ll focus on a few key points:

• Nehalem will incorporate CSI (Common System Interconnect), Intel’s HyperTransport response now renamed by marketing as the QuickPath Architecture.
• Nehalem’s ‘multi-level’ cache architecture, I’m suspecting in interpreting a somewhat nebulous response Smith gave to a question I asked, will be tri-level (at least in its quad-core variant) as is the case with AMD’s ‘Barcelona’
• Again as I interpret Smith’s intentionally vague reply to another attendee’s inquiry, Nehalem will support octal core configurations by means of dual-die packaging
• More SSE4 instruction set enhancements. Intel seems uninterested in accepting AMD’s invitation to join the SSE5 party
• HyperThreading’s back! Each core will process up to two simultaneous threads, albeit presumably only if one is integer-based and the other is floating point-centric.
• We’ll finally see integrated DRAM controllers on Nehalem, ironically responding to a feature that AMD’s offered (albeit with tradeoffs…it’s difficult to be nimble to DRAM industry technology and speed bin progressions when your response must await a full-blown CPU redesign) since its first Athlon 64.
• And some Nehalem variants will also include integrated graphics controllers, a preferable approach in conjunction with integrated DRAM controllers in unified graphics-plus-system memory configurations.

To summarize, Intel’s strategy seems to be firing on all cylinders:

• 2007’s ‘tick’ is the 45 nm process
• 2008’s ‘tock’ will be Nehalem, and
• In 2009, it’s back to the 32 nm process ‘tick’

How quickly and how forcefully will (and can) AMD respond in the face of Intel’s shock-and-awe (or if you prefer a previous war analogy; blitzkrieg) onslaught?