Freescale's ARM-based Kinetis Is Released: Did ColdFire Just Get Deep-Freezed?

Greetings from the Freescale Technology Forum in Orlando, FL. The company’s ARM Cortex-M4-based Kinetis architecture, which I first heard got briefed on under non-disclosure back at the Embedded Systems Conference Silicon Valley, is finally public news. And after hearing the pitches earlier this morning from Reza Kazerounian (Senior Vice President and General Manager, Microcontroller Solutions), Aiden Mitchell (Director of Industrial and Multi-Market MCUs) and Jeff Bock (Global Marketing Manager, MCUs) earlier this morning, backed by a brief plug from ARM’s CEO Warren East, my gut feel from late April remains…industry-standard ARM seems to be the focus-for-future for Freescale, while company-proprietary ColdFire architecture is best-case in ‘coast’ mode going forward.

Admittedly, ColdFire’s not going away any time soon. The customer base is mature and extensive, and the company just unveiled a 90 nm litho-shrink plan a few weeks ago. Keep in mind, too, that this isn’t Freescale’s first engagement with ARM; the company’s i.MX application processors have for years employed ARM9, ARM11 and Cortex-A8 CPU cores. But ask yourself why Freescale bothered expanding beyond PowerPC and ColdFire in the first place. As Jeff Bock said just a few minutes ago in the press briefing, “We’re happy if our customers pick ARM. We’re happy if our customers pick ColdFire. We’re happy if our customers pick Freescale.”…followed shortly thereafter by a plug for how straightforward the company’s and partners’ toolsets enable CPU architecture migrations.

Consider the relative schedules. Freescale unveiled ColdFire+ on June 8, saving Kinetis for the show. This was the case even though Kinetis samples will get to alpha customers first…in Q3, versus Q4 for ColdFire+, with both architectures expanding to general sampling in the nebulous ‘1H 2011′. Consider, too, the relative number of product proliferations that’ll come out of these two news releases…more than 40 new ColdFire+ variants, which sounds impressive until you compare that to the more than 200 new Kinetis variants the company plans.

Why Cortex-M4, which augments the more mature Cortex-M3 with DSP function enhancements such as a single-cycle MAC, SIMD extensions and a single-precision FPU? As former EDN technical editor Robert Cravotta (who I bumped into just a few minutes ago) points out, it’s about differentiation; Cortex-M3 overlaps ColdFire too much. But ironically, Freescale’s own foil set pointed out several times that ColdFire+ and Kinetis were both aimed at 50-200 MIPS performance-requiring applications. They also contained careful wording that suggested ColdFire would going forward be promoted for specific application-specific opportunities, whereas Kinetis was more appropriate for broad adoption.

Anyway, at the 90nm process node, the incremental die size needed to implement the incremental Cortex-M4 feature set above a Cortex-M3 foundation is probably minimal. To that point, as I pointed out to Robert, if Freescale needed to quickly unveil a Cortex-M3-based product for competitive reasons, it could do so by disabling (or simply just not documenting) the added Cortex-M4 capabilities, much as graphics vendors create multiple product proliferations (at least in the short term) from a single silicon platform.

And why the big promotion push now, when general sampling is likely around a year away? That’s probably because NXP is already showcasing working silicon on its first Cortex-M4-based products, and other ARM licensees are reportedly also well along with their Cortex-M4 embedded controller projects. Freescale’s in catch-up mode, and it’s doing everything it can to present a here-now face to the public, whereas reality is more like coming-soon, or perhaps even coming-later.

I’ll close with a few comments on the TFS (thin-film storage) embedded flash memory which is a key attribute of the 90nm process node on which both Kinetis and ColdFire+ are based. Its vigorously promoted characteristics include a claimed erase cycling capability of more than 4.4 million cycles, along with a segmented-block approach that differentiates between main memory for the bulk of system firmware and a flexible memory partition for additional firmware, EEPROM emulation, or both. Note the key word ‘emulation’ in the prior sentence. This isn’t true EEPROM; as Freescale admitted to me at ESC Silicon Valley, it uses media management algorithms to mimick EEPROM functionality with traditional flash memory. Doing so provides for capacity flexibility, but it has downsides as well; non-deterministic write performance, along with a tradeoff between emulated capacity and cycling reliability.

What think you, readers; does Freescale’s Kinetis announcement represent a broadening of the product portfolio…and if so, can the company realistically be expected to continue to adequately service its existing customer base and product portfolio in the face of more than 200 new products built on a new CPU foundation? Or, instead, does it suggest a perhaps gradual but undoubtedly inevitable redirection away from ColdFire and to ARM for embedded control?

Below are a few photos I snapped of this morning’s media presentation, sequentially ordered as the foilset was chronologically pitched. Apologies for the low resolution; I haven’t yet upgraded my handset, so please zoom in to discern the details: