25nm 3-Bit-Per-Cell MLC: Will SSDs Provide A Home For Intel And Micron's Latest NAND Flash Memory?

Enterprise-targeted SSDs weren’t the only thing that Micron shared with me in recent days. The company also gave me an in-advance NDA heads-up on the news it jointly released with Intel yesterday morning; the partners’ shared technology development and high-volume manufacturing resource, IM Flash Technologies, is now sampling 3-bit-per-cell flash memories based on process technology the two companies unveiled at the beginning of February. At first I was confused; didn’t the companies already roll out 3bpc flash memory, around a year ago?

As it turns out, my recollection was close to the mark but not exact…the prior unveiling was 34 nm process-focused and coincident with last year’s Flash Memory Summit, whereas this one is 25 nm-tailored and timed to get the jump on this year’s conference. And although last year, Intel and Micron seemed bound and determined to get 3bpc 34nm-based products into production, my Intel contact now assures me:

Intel announced that as a technology milestone and did not have plans to productize the 3bpc on 34nm (they said that at the time). The 3bpc on 25nm has more of a manufacturing lead than the previous gen on 34nm, so they focused on 34nm MLC [editor note: 2bpc] product development last year and have plans to productize the 3bpc on the 25nm where they will have more of a competitive lead and stronger cost-competitive advantage.

Before continuing with the analysis of today’s news, here’s a timeline for reference:

• Intel announced its first SSDs, based on 50 nm SLC (single level cell, i.e. 1 bpc) and MLC NAND flash memory, back in August of 2008. I tested them later that same year, in both consumer and enterprise variants.
• Micron had unveiled its 50 nm-based first-generation ‘100′ series SSD product in late 2007, but that particular line never went into mass production. The follow-on ‘200′ series, which was also based on 50 nm NAND flash memory and which also saw only limited manufacturing volumes, was presented to the public in early August 2008, a few weeks before Intel’s announcement.
• Intel and Micron had previously unveiled 34 nm NAND flash memory in late May 2008, but the companies chose to focus on already-in-production 50 nm technology for their first SSDs.
• The 3bpc MLC variant of the 34 nm NAND flash memory was let loose, as I mentioned above, one year ago. The link to my colleague Suzanne Deffree’s writeup is above; here’s my piece published that same time. Was it a feasibility-only prototype from the get-go? Initially targeted for production, with a later change of plans? Something in-between those extremes? We’ll probably never know…
• One month prior, in late July 2009, Intel had rolled out second-generation SSDs based on 2 bps MLC 34 nm NAND flash memory, but the company skipped the SLC variant of the 34 nm technology.
• Micron followed Intel with 34 nm 2 bps MLC NAND flash memory-based SSDs in early December, although as my recent writeup noted, multiple firmware stumbles delayed their production ramp until May of this year. Note that, unlike Intel’s SSDs, Micron’s devices support SATA’s currently-highest-speed 6 Gbps burst transfer rate option, thereby in part rationalizing their delayed arrival versus Intel’s counterparts.
• Micron released its 34 nm SLC NAND flash memory-based enterprise solid-state drives last Friday, and
• As mentioned above, 25 nm SLC and 2bpc MLC NAND flash memory was unveiled by the IM Flash Technologies partnership six-plus months back.

As of yesterday, we now have the 25 nm 3 bpc MLC product, with all of the strengths and shortcomings of its 34 nm predecessor as noted in detail in my year-old piece…multiplied, in both cases. Its inherently smaller transistor-dimension foundation gives it even more cost-effective appeal from a bits-per-silicon real estate standpoint. But that same dimension reduction makes it an inherently more fragile transistor, both to temporal leakage and other charge-disturb effects which would alter the subsequently sensed bit value(s) previously stored to it, along with more permanent potential damage caused by various voltage-induced effects.

Where will Intel and Micron sell this monetarily attractive but inherently unreliable semiconductor material? USB sticks and memory cards of various form factors are likely candidates, since they tend to be write-once throw-aways in many application scenarios, and since fractions-of-cent cost savings are paramount to profitability in such high-volume scant-margin situations. But I’m going to go out on a limb, contradicting others’ predictions, and forecast that it’ll also end up in SSDs.

I’m feeling more than a bit of irony as I type these words. After all, it was just one week ago that Micron’s Dean Klein was admitting to me that his company’s delay in rolling out the enterprise-targeted P300 SSD series had to do not only with confirming that the consumer SSD-derived firmware was corruption-free but also in ensuring that the drives would meet corporate IT’s reliability expectations…and he was talking about 34 nm SLC-based products at the time.

However, I don’t underestimate the potential for human creativity, coupled with an abundance of EDAC, to effectively counteract inherent semiconductor limitations. And as last November’s cover story pointed out, per-transistor write performance limitations can be counterbalanced by clever media controller design coupled with multiple parallel array access paths (at the tradeoffs of higher power consumption and larger write payload granularity).

My other key tipoff as to what I believe Intel and Micron’s plans are, I admit, comes from not-entirely-reliable information sources. As reported by Engadget on Saturday, with subsequent pickup by Slashdot and others, a leaked set of seemingly legitimate slides gives insight into not only Intel’s CPU roadmap but also the company’s SSD aspirations:

Look at the 34nm- to 25nm-based per-device capacity jump, at comparable form factors. Now consider the corresponding cost pressure, versus other SSDs and (perhaps more importantly) versus the HDD alternative. Even if HDDs have over-shot most users’ capacity needs, they still define the cost-per-GByte metric that customers will expect SSDs to continue to chase. I don’t think Intel (and Micron, who presumably has similar plans) will be able to accomplish both objectives at 25 nm without moving from 2 to 3 bpc MLC NAND flash memory for consumer SSDs, and without migrating enterprise drives from SLC to at least 2-bit MLC NAND flash memory.

Place your bets. We’ll know the outcome within the year, I’d wager.