DesignCon 2012: 3D IC standards, great! But do we care?

DesignCon 2012 at the end of January many interesting panels, not least of which is, “Why do we need 3D design standards.” However, as cutting edge and exciting as that sounds, it may be asking the wrong question. The right question may be, “Do the economics of 3D make sense and who takes the fall when things go wrong?”

Much has been written about 3D IC packaging, most recently we discussed it in “EDA tools pave path to 3-D ICs” (EDN, June 9, 2011). But as the old saying goes, “when all’s said and done, there’s more said than done.” With regard to 3D ICs, alas, this is particularly the case.

A recent chat with Chi-Ping Hsu, (Ph.D), senior vice president of Cadence’s Silicon Realization Group, summed it up. While acknowledging it makes sense in certain applications such as mobile devices, and with vertically integrated manufacturers such as Intel, elsewhere, the problem comes down to the almighty dollar-and the blame game.

“Why [do it]?” asks Hsu. “Who is accountable and who makes the money and at what stage?” Given that different silicon sources have different ways of manufacturing through-silicon vias (TSVs), “Who’s fault is it when you have three die and it doesn’t work?”

Chi-Ping Hsu

There are many other issues, including the handling of fragile known good die (KGD) and rework when things do go awry. With multichip modules, the handling of KGD was a problem, but you could at least swap out a module if it was defective. That’s not so easy with tightly packaged die with 10,000 interconnects per die.

For now, according to Hsu, 2.5-D technology with bumped die on an interposer with associated logic is the way to go as it allows for rework and avoids the economics and the blame game.

Hsu’s pragmatism led us quickly down the path to a brief discussion of more practical solutions to today’s problems, and to what may have been one of the most under-hyped announcements of the year.

While all media eyes were on 3D IC design earlier this year, Cadence was continuing to update Virtuoso IC 6.1, which includes the Open Access (OA) database. Up until 6.1 and OA, the Cadence Data Base (CDB) had been used, so with the move to OA, design teams could save data in a common format usable by other EDA vendors’ tools. (Caveat: OA was developed by Cadence and donated to the Silicon Integration Initiative (Si2).)

According to Hsu, the move to OA is a move to a new generation of technology that moves designers from connectivity-based design to intent-based design by abstracting them from the details underneath. “We want designers to focus on creativity versus engineering.” The end result is a 40% savings in project time, according to Hsu. Now that’s useful!
Of course, it does raise questions as to what’s really required of students preparing for the workforce, but that’s a separate discussion.

So, while 3D may not be ready for prime time, and EDA companies — wisely I might add - focus on problems resolvable and practical in the here and now, the DesignCon panel does explore a key issue for 3D enablement, namely the need for IC standards to accelerate the adoption of 3D design. It’ll look at how the standards can be implemented, the priority of those standards, the challenges and how the industry is meeting those challenges.

If that whets your appetite, the conference features a whole track dedicated to analog and mixed-signal design and verification, as well as tracks on system co-design (chip, board, package), and chip-level design for signal and power integrity.

The panel on 3-D standards is part of the system co-design track and features as speakers Sumit DasGupta (Si2), Liam Madden (Xilinx) and Raj Jammy (Sematech).

I’ll be at this year’s conference, held, as usual at the Santa Clara Convention Center (January 30 to February 1). I’m going to look for both cutting-edge explorations as well as practical solutions to real-world problems. How about you? See you there?

Patrick Mannion (@patrick_mannion, or patrick.mannion@ubm.com)