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Fab 5

March 1, 2009

For some time I have been talking about the semiconductor industry as the Fab 5, since there have been five process “clubs”. A few players hedge their bets and are in more than one club. The fab five are Intel (a club on its own), UMC (along with Xilinx and Texas Instruments), IBM (along with Samsung, ST, Infineon, AMD, Sony, Freescale and Chartered), Japan Inc (Renasas, Toshiba, Fujitsu, OKI, Sharp, Sanyo, Matsushita) and the big one TSMC (with AMD, TI, NXP, ST, LSI, Sony, Qualcomm). Japan Inc in particular is messy with Toshiba tied closely to NEC (in the TSMC club) but to Sony (in the IBM club too), Renasas and Fujitsu are still sort of going it alone. Japanese politics would indicate that they will all get together somehow.

Big changes are afoot. Here are some of the things going on, ST, NXP and Ericsson wireless are all merged together into a new company (called, yawn, ST-Ericsson). Nokia has also sold its wireless unit to ST so it is presumably in there somewhere. Toshiba looks like it is going to really join Japan Inc (as if there was any doubt). TI and Freescale are both trying to find a home for their wireless groups but nobody wants them at a price they want to sell. The IBM club have deepened their technology agreements and ARM (although fabless) seems to be sort of joining the IBM club to help create energy-efficient SoCs, with Samsung both building and consuming the volume (and so I hereby rename the IBM club the Samsung club).

What about everyone else? AMD, ATI (also in AMD for now), MIPS, nVidia, UMC, NXP, Infineon, Motorola, Texas Instruments, Freescale were all bleeding cash even before the downturn got really bad, and they are reducing their footprints. All of Japan Inc except maybe Toshiba were also bleeding money (and Toshiba would have been except for all that flash going into phones and iPods, and is now hurting more after losing Xilinx to Samsung over price).

So based simply on financial strength it looks like the 3 fabs are going to be TSMC, Intel and Samsung (taking over the name badge for the IBM club) long-term. Of course other people like ST won’t lose their fabs overnight but they won’t be able to afford to keep up. And it is unclear how many of the memory houses will make it through the current downturn. Qimonda is clearly comatose already and isn’t going to wake up.

So the Fab 5 will become the Fab 3. For EDA this just emphasizes that there are too many EDA companies, as I’ve said before. Or maybe that EDA will go internal again, which is a discussion for another day.

Who would have predicted 20 years ago when TSMC was a small foundry with a non-competitive Philips process that it would be the dominant player. Kind of like predicting that Ringo would be the last Beatle of the Fab 4…oh wait, maybe that’s going to happen too.

Posted by Paul McLellan on March 1, 2009 | Comments (6)

March 4, 2009
In response to: Fab 5
bayareadude commented:

Your foundry planet graph is a bit off, but captures the essence. The consolidation on the fab space actually makes life for EDA easier... fewer technologies to support. TSMC, with it's reference flow and proprietary formats for DFM is driving differentiation, but other than Blaze, has been largely neutral.


March 2, 2009
In response to: Fab 5
Delico Vermonty commented:

Seems to me that foundry specific tools are going the way of the dinosaur. I used LSI tools a long time ago and also used IBM tools for doing 3 ASICs with them. All had weird idiosyncrasies and, of course, locked you into a single supplier. As a engineer one is better off learning horizontal tools as Grant suggests, since there is no guarantee that your next project or employer will be with the same foundry.


March 2, 2009
In response to: Fab 5
Grant Martin commented:

Indeed, as SteveM commented, the reason for such a re-integration of EDA (back end) and Fab will no doubt be when, and if, there is strategic advantage (for example, yield improvement = cost reduction for the fab) that would differentiate one fab over another. And if yield improvement is not done just at the last stages of the back end, but has deep interactions higher up the flow, then this might happen if there is some interesting breakthrough there. So this possibility will depend perhaps on some real innovative breakthroughs in what EDA algorithms can do - breakthroughs that make it worth it to privatise what is now a more open oligopoly.


March 2, 2009
In response to: Fab 5
SteveM commented:

Martin - Semiconductor co''s view EDA like auto co''s view auto parts and steel companies. The horizontal stack disaggregation (horizontalization) is working perfectly for them. They have an open market with interoperable standards and hold regular open benchmarking to drive competitive performance and pricing. This lets them focus on their specialties and command premiums for their product. What''s not to like ? Externally EDA companies can try serve all the fab clubs and can hope to gain a dominate market share. The trigger which will make your idea take root is when a foundry develops the strategic view that with EDA can offer a unique differentiated product to their customers which will yield them more customers at a higher premium. It''s much easier for a semi CAD manager to manage external firms rather than internal firms. If the technology doesn''t deliver he can just throw his vendor under the bus rather than be personally responsible. Meanwhile he gets free tickets to the ball game and golf outings to boot. IBM is the last of the internal (back-end) CAD species ... so time will tell whether this fab club excels with this unique trait.


March 2, 2009
In response to: Fab 5
krylov_subspace commented:

Dr. Martin Reading your blog with interest here in India. Would you care to comment on the following question ? Should TSMC come up with its own STA tool for signoff? It is a question many of my acquaintances have asked. It it might relieve the customer from the deadly claws of SNPS and its Primetime. TSMC can easily do a better job than SNPS and have a far better understanding of interconnect physics like inductanctance extraction with accuracy and stable numerical methods and ditto for capacitance. Likewise for DRC/LVS. EDA engineers do not necessarily write the best code. Almost all EDA code is buggy and they are sold with the expectation that they will fail in a real tapeout.


March 1, 2009
In response to: Fab 5
Grant Martin commented:

One theory for idle speculation - which I wondered about several years ago - was whether the Fab clusters (clubs in Paul's analysis) would eventually be equivalent to the number of EDA companies with back ends (RTL to GDS II in the old days, now including no doubt mask manipulation etc.). Arguably there are 3.5 of these companies if you think Mentor has .5 of a back end flow with Sierra - or at least 3 - Cadence, Mentor, Synopsys. And Intel probably doesn't need EDA for its back end, as If the fab clubs end up equalling the number of EDA back ends, wouldn't they save a lot of money by each privatising the back end - by buying out one of the EDA companies, keeping the back end R&D, getting rid of the enormous overheads of marketing, sales etc., and spinning back out as small EDA companies the front end bits (like simulation, etc.). Certainly, this was worth an idle speculation or two over lunch several years ago. What might happen now?

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