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Ferrari vs Formula-1

February 4, 2009

It used to be received wisdom that the way to get a good design flow was for a semiconductor company to purchase best-in-class point tools and then integrate them together themselves. I think there were two reasons for this. First, the EDA companies had grown from a lot of acquisitions so that’s what they had for sale: good point tools that were poorly integrated. Second, they were selling to CAD groups in an era when semiconductor was doing well and CAD groups liked to justify their existence by doing lots of evaluation (which point tool is best?) and then integrating them (need lots of people).

For most people, this was actually not the best way to get a productive environment matched to their needs. It is as if we all had to buy cars the way a Formula-1 team does, buying the best engine, the best brakes, the best gearbox and making everything work well together ourselves at great expense. If you really need to win a Formula-1 race then this is the only way to go. Even a top of the line Ferrari is simply way too slow. But for most of us, a Honda Accord is just fine, easier to use, cheaper to acquire, and orders of magnitude less expensive to get and keep on the road.

Back in that era I was at VLSI Technology. When we spun out Compass we had a Honda Accord in a marketplace where people thought they wanted to build their own Formula-1 racecar. Potential customers only wanted to benchmark point tools and wouldn’t even attempt to benchmark an entire design flow. I’m not even sure how you would. I don’t know how much better the design flows that CAD groups assembled out of Cadence and Synopsys point tools (along with a seasoning of stuff from startups) really were. And neither does anyone else. They were certainly incredibly expensive in comparison. Before the spinout, I made several visits to semiconductor companies whose CAD groups were bigger than VLSI’s Design Technology group. But Design Technology developed all the tools, wrote all the source code for synthesis, simulation, timing analysis, place and route, physical verification, designed all the standard cell libraries, created the memory compilers and the datapath compiler. Soup to nuts. I think the only external tool in wide use was for gate-array place and route, an area where VLSI was never that competitive anyway (if you really wanted a gate-array, you went to LSI Logic).

Magma was the first and only EDA company to build an integrated environment. A CAD manager friend of mine told me that they used Magma for everything they could. For the most difficult designs they used Cadence’s Silicon Ensemble but they could train someone on Magma in a day (and they weren’t immediately hired away by the competition once they’d been expensively put through training).

At the EDAC forecast meeting a couple of weeks ago, Aart de Geus said he has been preaching that an integrated flow is important for years. One difference he is noticing in the current downturn, he said, is that this time executives are listening. Chi-Ping Hsu of Cadence told me the same thing about the Cadence PFI initiative which was well-received by power-sensitive customers (is there another sort of customer?). PFI’s main thread, the CPF standard, pulled together tools from across Cadence’s product line along with standards that allowed external tools to play in the flow too. Synopsys UPF does the same thing on their side of the standard wars trench. People had managed to put together power-aware flows before, lashing together point tools with lots of their own scripts. But they were very buggy and many chips failed due to trivial things like missing isolators or not taking getting the timing right in multi-voltage blocks. This seems to be a thing of the past now, although most designs are still on the basic end of power saving (fixed voltage islands, power-down) and not yet attempting the really tricky things like dynamic voltage and frequency scaling (lowering the voltage and slowing the clock when there is not much to do).

In the current hyper-cost-sensitive environment I think that the pendulum will swing back the other way towards these more pre-integrated flows and away from the integrate-your-own-point-tools approach. It is also the only way that complex factors like power, that cut across the whole design flow, can be accommodated. The slowing of startup acquisitions by the majors feeds into this, giving them time to put the effort into integration without constantly gaining more things to integrate. The integration has enormous value despite the fact that customers have been historically reluctant to pay vendors for it. When I was at Cadence we had some research showing customers spent $3 or so on integration for every $1 that Cadence got. So customers were paying for it, just not externally.

Not exactly on-topic, but you can actually see a Formula-1 car race a Ferrari and a Fiat.

Posted by Paul McLellan on February 4, 2009 | Comments (14)

December 12, 2009
In response to: Ferrari vs Formula-1
laptoplover commented:

Hey are you a professional journalist? This article is very well written, as compared to most other blogs i saw today?. anyhow thanks for the good read!


February 19, 2009
In response to: Ferrari vs Formula-1
SudzyTheClown commented:

I'd like to point out a little study from Gartner that shows that the number of ASIC design starts halved during the last recession (the dot.com bust) and has continually declined since then. Considering that was before DFM and $30 million mask sets, what do you think ASIC starts will do this time? Last time, the recession was restricted to communications and related apps. This one is communications and everything else? What will that do for ASIC starts? What will it do to EDA starts? EDA was strong during the last recession. It was already ill going into this one. $1 to $2.5 per share for 3 of the 4 biggest EDA firms. All-in-one flows vs build your own doesn't matter if you only have 5 or less customers, who can afford to create chips on the latest processes? Is there any chance we'll see ASIC design starts rocket back to 20k starts per year?


February 19, 2009
In response to: Ferrari vs Formula-1
Cheapskate commented:

C'mon folks, In this economy everyone is going to have to target the EDA "Hondas" (or "Chevrolets"), vs. the mix and match Formula 1's most of the commentators seem to dream about. Unless your custom-developed EDA flow and special IP give you hugely differentiated end-results, commercial EDA flows and IP are cheaper both short term and long term. Even Intel and IBM, long bastions of internal tools & flows, are realizing the reasonable capabilities and superior economics of commercial flows. If you are going to dream, enjoy the Formula-1's, but if you need to actually buy something, it's likely your boss really wants you to drive the Honda.


February 8, 2009
In response to: Ferrari vs Formula-1
EDAExec commented:

Paul naively assumes that all EDA tools come from EDA vendors. In fact, I know of NO semiconductor design group that does not use some form of internal or proprietary tool or IP in their flow. The sad truth is that EDA vendors CANNOT deliver a complete, integrated flow. So, by definition, Paul's point is not valid ... companies must integrate their own tools. Most EDA pundits believe the future is returning to the '70s era where companies will actually invest and find great value in internal CAD teams. Here comes those days again ... in fact, isn't Magma just a commercialization of IBM's internal tools when the pendulum swung in the '90's to downsizing internal CAD tools because the belief was EDA vendor's could deliver an entire flow? If the pendulum DOES swing back to the era of the vendor's creating their own, large CAD teams, then EDA startups with best-in-class tools will again FLOURISH, not disappear as predicted lately. Let's hope it's is indeed the case ... else we'll all be subordinate to Aart and his hencemen.


February 5, 2009
In response to: Ferrari vs Formula-1
wieslaw commented:

Thanks Paul for remembering exciting Compass times! We made first sales of Compass tools to Russia thanks to ?all in one? nicely integrated full solutions!


February 4, 2009
In response to: Ferrari vs Formula-1
DeanS - www.foresightsystems-mands.com commented:

I always worry when I disagree with Mr. McLellan, but this time I find myself in that position. I do not believe that proprietary "walled garden" type flows from the leading EDA vendors will actually solve many problems, including for those vendors. I also don't think that they'll actually be able to pull it off. Instead, I side with Mr. Payne in believing that one flavor of flow will come from system integrations into open frameworks. For this to happen, vendors with strong point tools and, perhaps, sub-flows, will need to support standard interfaces / exchange formats. While the vendors may resist that now, powerful customers are going to force the issue. I believe that we will see increasing pressure from foundries (who will invest in integrating complete tool flows that target their processes) and from the really powerful semiconductor companies (who are doing in-house integrations to complete proprietary flows made up of point tools). Once enough pressure is applied to get some level of "openness,? we'll start to see multiple sources for flows -- the big EDA vendors, the foundries, the big semiconductor companies and a new breed of design flow systems integrators.


February 4, 2009
In response to: Ferrari vs Formula-1
ImaNobody commented:

Could it possibly be that the reason Cadence and Synopsys are the ones advocating this approach is because they feel they have the most complete solution, and not necessarily the best solution. How's ICC doing these days versus Atoptech/Sierra/SOCE? How's RTL Compiler doing against DC? I'm gonna guess if I told Cadence I'm dumping SOCE for ICC because I'm a DC user, they will change their tune. This is quite simply FUD to deal with some startups who have decent tools.


February 4, 2009
In response to: Ferrari vs Formula-1
user commented:

What is required is integrated best-in-class software, not just integrated or best-in-class software. It sometimes appears like some EDA vendors are forgetting this.


February 4, 2009
In response to: Ferrari vs Formula-1
Aaron commented:

I was hoping to read about Ferrari and F1!


February 4, 2009
In response to: Ferrari vs Formula-1
FactMan commented:

Whereas CPF is a Cadence format, UPF is not a Synopsys format. It is an industry standard format created by a broad coalition of companies, including Mentor, Magma, Synopsys and many other EDA companies and design houses.


February 4, 2009
In response to: Ferrari vs Formula-1
SteveM commented:

This argues against current point tool startups like Azuro, Pyxis, and in favor of the full flow companies (Cadence and Synopsys). It is true that the ROI of funding a CAD team as well as opportunity cost is likely not a good tradeoff. Although customers will want a flow to drive competition to keep the market innovation alive. This leads to two 'proprietary' flows with lack of integration. OA was supposed to drive openness, but only seems to have brought new competion for Cadence in analog. So there will be endles Synopsys/CDN flow benchmarking moving forward. We'll see if Mentor can swim against the tide with Pinnacle/Olympus.


February 4, 2009
In response to: Ferrari vs Formula-1
Maestro commented:

Unfortunately the concept of EDA (and even its lexicon) started around "automation". Nevertheless, IMHO the reality has always been that EDA is there for risk reduction. I.e. if you get a verification tool that runs 2x faster, you don't necessarily cut your verification timeline by 2x. You'd spend the same effort on verification and just make sure you are finding/fixing more bugs. So if you take out "automation" as the real driver for design tool usage, it becomes quite moot to benchmark point tools .... Who really cares if a synthesis tools runs 30% faster and gets you the same result within 3% of its competitor?!! A lot of CAD groups fell under that confusion. If you focus on "risk reduction", there would be no argument that an integrated tool set significantly limits the overall risk. As an anecdote, at VLSI we had a high first-silicon success rate (i.e. no respins). Those chips were designed on an integrated tool set (Compass). I can't remember the exact first-silicon percentage we had (it was above 90%), but I personally haven't been associated with higher rates since.


February 4, 2009
In response to: Ferrari vs Formula-1
Daniel commented:

Mentor did at one time start from scratch to create an integrated flow and called it Falcon or 8.0 - what a financial and technological letdown. It is what knocked the former number 1 EDA company into it's present number 3 position. They tried to make an integrated, but closed design flow. Today, we want integrated but open design flows. Mentor has since given up on Falcon and instead offers excellent point tools and subflows. Live and learn. www.marketingeda.com


February 4, 2009
In response to: Ferrari vs Formula-1
bayareadude commented:

No doubt that integrated is the way to go, but doing it is not as easy as it sounds. But integrated posts a whole new set of challenges that most EDA development teams aren't up for. Most EDA development teams do not have the training or discipline to efficiently manage code from 100's of developers... so the downsides of schedule slips, code quality (bugs and performance) creep in. The fast pace of development needed for IC design (new nodes every 18 month) compound this. What Magma did right is start from scratch; something Synopsys and Cadence did not do. But keeping the integrated beast moving after 10 years is impossible, so deciding how/when to rewrite the major engines is as much art as it is science. So don't write off the point tools yet...

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