Internal development
One potential change to the way chips are designed is for EDA to become internal to the semiconductor companies. In the early days of the industry it always was.
Until the early 1980s there wasn’t really any design automation. There were companies like Calma and Applicon that sold polygon level layout editors (hardware boxes in those days) and programs like Spice and Aspec that were used for circuit simulation (and usually run on mainframes). Also there were a couple of companies supplying DRC software, also typically run on mainframes.
In the early 1980s, companies started to develop true design automation internally. This was implemented largely by the first set of students who’d learned how to design chips in college as part of the Mead and Conway wave. Hewlett-Packard, Intel and Digital Equipment, for example, all had internal development groups. I know because I interviewed with them. Two startups from that period, VLSI Technology (where I ended up working when I first came to the US) and LSI Logic had ambitious programs because they had a business of building chips for other people. Until that point, all chips were conceived, designed and manufactured internally within semiconductor companies. VLSI and LSI created what we initially called USICs (user specific integrated circuits) but eventually became known, less accurately, as ASICs (application specific integrated circuits). It was the age of democratizing design. Any company building an electronic product (modems, Minitel, early personal computers, disc controllers and so on) could design their own chips. At this stage a large chip was a couple of thousand gates. The EDA tools to accomplish this were supplied by the semiconductor company and were internally developed.
First front-end design (schematic capture and gate-level simulation) moved out into a 3rd party industry (Daisy, Mentor, Valid) and then more of design with companies like ECAD, SDA, Tangent, Silicon Compilers, Silicon Design Labs and more moved out from the semiconductor companies into the EDA industry.
At first the quality of the tools was almost a joke. I remember someone from the early days of Tangent, I think it was, telling me about visiting AT&T. Their router did very badly set against to the internal AT&T router. But there was a stronger focus and a bigger investment behind theirs and it rapidly overtook the internal router. Since then almost all EDA investment moved into the 3rd party EDA industry. ASIC users, in particular, were very reluctant to use tools that tied them to a particular silicon manufacturer since they didn’t want to get locked-in for their next design. Since every semiconductor company wanted to get into ASIC (even Intel had an ASIC group) and the ASIC flow was pretty much standard (gate-level handoff and back-annotation) the market exploded.
ASIC, in the sense of designs done by non-semiconductor companies, has declined as levels of integration have gone up (what was 5 chips is now 1) and as most designs that are not power-sensitive have moved to FPGAs. So once again most designs are done inside semiconductor companies where being “locked-in” to in-house tools would not be an issue.
The EDA industry invests approximately 20% revenue in R&D. Maybe even 35% if past acquisitions were properly accounted for. So there is somewhere around a 3 to 5 times cost disadvantage. Also, it is generally accepted that producing a generalized supported software product is at least 3 times (and maybe much more) expensive than just developing a product for internal use. With approximately 3 serious competitors in each tool segment, the EDA industry needs to take about 30 times as much money from the semiconductor industry as it would cost a semiconductor company to develop a tool internally. That is 3 tools being developed, each at a cost 3 times the internal development, with selling price of 3 times the cost of development. This is significant since the number of large semiconductor companies purchasing tools is also declining as they consolidate and/or run into financial trouble. It is too early to call predict exactly how that will pan out.
There is today no market for specialized tools for microprocessor design. The tools are all internally developed. It is certainly arguable whether it would be possible to produce a general tool but the economics would not work in any case. There simply are too few microprocessor design groups to pay the tax of the EDA industry generality, overhead and profit.
There is no real market today for tools for FPGA design. The tools are all (OK, mostly) internally developed. But the economics wouldn’t work when there are only 2 or 3 FPGA vendors. It is more economic for each vendor to develop their own suite (not to mention that it better fits their business model).
One future scenario is that all semiconductor design becomes like microprocessor design and FPGA design. Too few customers to justify an external EDA industry, too specialized needs in each customer to make a general solution economic. Design moves back into the semiconductor companies. I don’t have much direct knowledge of this happening, but Gary Smith is always pointing out that it is an accelerating trend, and he sees much better data than I do.
One other issue is that for any design tool problem (such as synthesis or simulation) there is only a small number of experts in the world and, by and large, they are not in the CAD groups of semiconductor companies, they are in the EDA companies. I predicted earlier that the world is looking towards a day of 3 semiconductor clubs. In that environment it is much more like the FPGA world and so it is not far-fetched to imagine each club needing to develop their own tool suite. Or acquiring it. Now how many full-line EDA companies are there for the 3 clubs? Hmm.
Jeremy Ralph commented:
BreadnButter commented:
Hardtruth commented:
Jeremy Ralph commented:
realhard commented:
SteveM commented:
realTruth commented:
Hardtruth commented:
Mark Gogolewski commented:
DumbIdea commented:
Daniel Payne commented:
