Subscribe to EDN

Analog Devices ADCLK954 and ADCLK854: Clock buffers have 75- and 100-fsec jitter

June 10, 2009

The 12-channel ADCLK954 LVPECL and the ADCLK854 LVDS/CMOS clock-fanout buffers provide 75- and 100-fsec jitter, respectively. The clock buffers have a 9-psec skew, suiting use in high-speed ADCs and DACs, wireless-infrastructure equipment, medical-imaging applications, and industrial applications. The 4.8-GHz ADCLK954 has two selectable differential inputs using the input-select control pin. Both inputs have 100Ω on-chip termination resistors. The clock buffers operation over a –40 to +85°C temperature range. The ADCLK954 comes in a lead LFCSP-48 with 12 or 24 channels and costs $5.95 (1000); the ADCLK954 comes in a lead LFCSP-40 package with 12 channels and costs $6.95 (1000).

Analog Devices, www.analog.com

Posted by EDN Staff on June 10, 2009 | Comments (0)
POST A COMMENT
Display Name
captcha

Before submitting this form, please type the characters displayed above. Note the letters are case sensitive:

Advertisement
Advertisement
Advertisement
About EDN   |   Site Map   |   Contact Us   |   Subscription   |   RSS
© 2012 UBM Electronics. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy

Please visit these other UBM Canon sites

UBM Canon | Design News | Test & Measurement World | Packaging Digest | EDN | Qmed | Pharmalive | Appliance Magazine | Plastics Today | Powder Bulk Solids | Canon Trade Shows