DPA tools and FPGA hacking vulnerability
The growing use of FPGAs in FIPS-140 applications, particularly in modules using mezzanine card formats, has sparked a growing interest in assuring the cryptographic security of an FPGA that implements keys in bulk encryption or digital signature applications. Our coverage in late October of the Virtex and Spartan involvement in SASEBO-GII (Sidechannel Attack Standard Evaluation Board) designs in Japan spurred interest from the developers at Cryptography Research Inc., who have spent a decade looking at vulnerabilities in smart cards that resulted from attempts to extract keys through analysis of a device’s power dissipation.
You heard right, two levels of power analysis employed by hackers – simple power analysis and differential power analysis (DPA) – can allow extraction of keys from simple monitoring of the power consumed by active microcontrollers used in smart cards. Cryptography Research spent years developing signal-processing techniques to offer on-chip countermeasures for ASICs and controllers. The company also offers a CryptoFirewall IP core and a DPA Workstation for those wanting to conduct detailed DPA studies in-house.
Benjamin Jun, vice president of technology at CR, said that his company has spent several months informally discussing power analysis of FPGAs with both FPGA vendors and their customers in high-security vertical markets. The company has worked with Japan’s National Institute of Advanced Industrial Science and Technology to insure compatibility of its tools with the SASEBO FPGA testing environment.
Of course, using DPA to extract keys from complex products like microcontrollers and FPGAs suggests the method is at least partially useful in performing rudimentary reverse engineering on complex logic devices. That is one impetus for Cryptography Research’s ongoing discussions with the Trusted Computing Group alliance, particularly in realms of device security surrounding the group’s Trusted Platform Module.
Jun stressed that the company is still in its initial stages of studying adjunct logic blocks that could be added to an FPGA design to serve the same countermeasure role that is now standard in smart cards. But as the FIPS 140-3 federal standards for secure computing move into final approval stages, the threat is moving upstream into more complex devices, such as high-end FPGAs.
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