The interface makes the FPGA

custody behavioral quantum birthplace kajumulo downturn roms kumarsandeep course wheeler utensils

I globally agree with what it said in the article. Nevertheless, I would add a few Interface protocols: - Ethernet: look at the partnership between Altera and MorethanIP (Ethernet MAC IP). This partnership is active since 2005 I guess - USB: for the previous release of USB (2.0 HS @ 480Mb/s), FPGA was not considered because it was a very price sensitive market (PC peripherals and Consumer). With SuperSpeed USB(5gb/s), because the ASIC prototyping cost have exploded for the latest technologies (40nm or 28nm), the option to develop a FPGA and access the market quickly and at a much lower development cost may valid an approach based on FPGA to test the market with a short TTM... then move to another solution (real ASIC, hardcopy or low cost FPGA family) for production cost. The USB 3.0 PHY is so close to PCIe Gen-2 that it should not be a technology issue on the High End FPGA families (Virtex or Stratix). The issue will be for a customer to be sure to find a low cost family for the production with USB 3.0 PHY integrated... the FPGA vendors have some homework to do. I know for sure that an IP vendor selling USB 3.0 Controllers has made some IP sales for FPGA technologies, there is customers who think that make sense to develop a product with SuperSpeed USB support on FPGA. - Finally, if you look at the FPGA startups like Achronix or M2000, they have based their product on Ultra High Speed I/O support, with Multi Protocol SERDES for: 40G/100G Ethernet CEI-6G 10 Gbps backplane XFI PCI-Express XAUI Serial RapidIO Just to say that High Speed I/Os are the present and the future for FPGA technologies, and that it is not restricted to PCIe, HT and Serial RIO! Interested into Interface IP, just have a look at www.ip-nest.com, you will find plenty of information... Infiniband

I/O also defined the market for FPGAs in 2005, 2006, 2007, 2008, 2009.... The FPGA is still a system afterthought, versus system critical core function. TI defines SRIO as the DSP interconnect and the FPGA dogs chase it down the street two years later. 1000 DSP resources on chip for an FPGA and it's still a PERIPHERAL device to a DSP. Intel does PCIe, the dogs wag their tails and define I/O, and soft/hard IP to support it. If I/O truly defined the market, we'd see FPGAs taking the lead in system partitioning and protocols. IMO it has yet, if ever, to do that in most relevant-systems that are out there.