Make Way for DDR3

Any thoughts that implementation of systems using DDR3 SDRAM might be delayed by either OEMs or microprocessor developers were eliminated this week when a colleague, Gordon Kelly, reported for Smartbook Blog that Intel would support the new memory interface in its next-generation Atom. The speed of adoption of video in small platforms has accelerated the desire to support the latest memory interfaces.

Sid Mohanty of Lattice Semiconductor provided an interesting example March 8 in Embedded.com of a video processing engine that integrates a DDR3 controller and video buffers, to handle four video streams at once. Obviously, whether the memory controller is resident on an FPGA or in a separate subsystem with special buffers may depend on how video streams are processed, but Mohanty makes a good case for using an efficient (and validated) IP block for the DDR3 controller.

In the ECP3 implementation Mohanty uses, optimization of the IP block for burst-mode performance and power management were critical. We’ll no doubt see many implementations in which a primary DDR3 controller makes more sense in a control-plane microprocessor, or in a single-chip or multichip video subsystem. But by demonstrating one possible FPGA implementation today, Mohanty has paved the way for an FPGA role in the DDR3 tsunami which will be hitting with some force later this year.