A new milestone for high-volume consumer FPGAs?

Since Lattice Semiconductor Corp. has been emphasizing performance aspects of the new ECP3 family, it is tempting to think of wireless infrastructure and similar applications where this device might play. Consequently, it deserves emphasis that Lattice aims its ECP series at the type of applications using Spartan or Cyclone devices – the company’s SC family is the competitor to Virtex and Stratix.

Shakeel Peera, director of strategic marketing for SRAM-based FPGAs at Lattice, said two critical factors distinguish ECP3 in the cost-sensitive device market: an early emphasis on Serdes-based I/O, allowing low-cost FPGAs to feature Serdes interfaces as fast as 3.2 Gbits/sec; and sysDSP cores allowing FPGAs in a $35 to $50 price range to compete in algorithm-intensive applications such as digital TV and Voice Over IP gateways.

The virtually flat power consumption escalation as lookup tables grow to 149,000 LUTs, assures that Lattice can aim the ECP3 architecture at low-power consumer applications. The combination of the low power dissipation and the sysDSP cores, supporting multiply and arithmetic logic unit functions, has won Lattice some 3G/4G customers among early-access partners. Affarii Ltd., for example, is using ECP3 to implement advanced functions such as Crest Factor Reduction.

Launching a rich feature set in the ECP3 family may turn the bulk of competitive activity at Xilinx and Altera away from their respective Virtex and Stratix families, and more toward Spartan and Cyclone. As feature sets improve in the mid-range and cost constraints take over as the primary drivers in 2009, will highest-end FPGAs lag as design activity turns to a cost-sensitive class of device?