Betwixt tick and tock

If you’re like me, Intel Corp.’s vastly expanding list of microprocessor code names long ago got too complex to assign any rational value to, let alone remember. A couple keynote speeches at the recent Intel Developer Forum helped straighten me out on the relationship between families. But perhaps more important, CEO Paul Otellini and EVP Sean Maloney laid out Intel’s tick and tock development strategy.

Perhaps this idea is commonly used among other large semiconductor powerhouses, though I’ve never seen it explained before. The pendulum swings of the design cycles would seem to allow a period for FPGA-based differentiation – if outsiders can synchronize to the Intel clock cycles.

Basically, on a tick sweep, Intel launches a process technology, but uses it to implement a familiar microarchitecture.. On the tock sweep, a new microarchitecture is launched using a feature size that is already semi-mature. Note that when tick comes around again, Intel can attempt to pack more functions into the design using an SoC approach, if the design warrants such further integration.

In explaining this cycle, Intel executives candidly said they could not provide all necessary peripheral functions to customers all the time, though they certainly try to be a one-stop shop. In fact, Maloney in particular warned that trying to launch a new microarchitecture in a new process node would be a recipe for disaster. First, you get familiar with 45-, 32-, or 20-nm design rules, then you experiment with new architectures, and only when those architectures are mature, do you move down in feature size. Notice this implies some breathing space betwixt tick and tock?

Right now, for example, the microarchitecture called Nehalem is being ported from 45 to 32 nm. Once Intel is familiar with 32nm and has had an opportunity to integrate, the company will move to a new microarchitecture called Sandy Bridge. And there are many similar examples in Atom and SoC worlds.

This suggests that FPGA vendors should watch Intel customers closely for those moments between generations. Intel often can offer high-integration peripherals. Or it can combine a 32-nm core processor with a 45-nm co-processor, on a unique substrate. But merely having so many elements in its bag of tricks does not make Intel invincible. FPGA vendors may be able to run under the pendulum.