Putting an FPGA in the RRH chain

It may not be news to place an FPGA close to an IF/RF interface in a handheld or base station design, but Lattice Semiconductor Corp. has taken integration a step further this week. The company announced on Oct. 26 a collaborative project with Affarii Technologies Ltd. on development of an integrated Remote Radio Head (RRH).

We have seen a handful of designs in Multiple-Input/Multiple-Output systems, used in WiMax access points and software-defined 4G base stations, in which an FPGA of a Virtex or Stratix class is used close to the antenna. Lattice’s innovation  was to leverage the expertise of Affarri to develop a more cost-effective RRH based on theECP3.

Affarii’s specific claim to fame was the development of digitalTRX processors and algorithms for implementation of digital pre-distortion (DPD) and crest-factor reduction (CFR). Consequently, the radio head in this case implements all DPD, CFR, and digital up- and down-conversion. The ECP3 FPGA also implements Ethernet interfaces and common base station profiles defined by CPRI/OBSAI (Common Public Radio Interface/Open Base Station Architecture Initiative).

The two companies are offering a demonstration platform that can scale to provide baseband support for up to two transmit and four receive antennas on a single chip, with each antenna supporting four carriers and 20 MHz modulation bandwidth. When the RRH is used with a Doherty amplifier, DPD can provide up to 30 dB of ACLR correction per transmit antenna.

Remember what we said about programmable DSPs disappearing from a range of RF/IF subsystems? If this keeps up, DSP-based ASSPs may be just as threatened in baseband designs as full-fledged DSP processors.