How much need for speed?

One obvious advantage of moving to a 40-nm process in Xilinx Inc.’s new Virtex-6 and Spartan-6 families is the ability to standardize very high speed I/O blocks. At a recent 25^th anniversary celebration, Xilinx’s director of product marketing Brent Przybus emphasized the GTH serial transceivers used in the Virtex-6 HXT family. Since up to 64 11.4-Gbit/sec transceivers can be integrated on a single HXT FPGA, the highest performing member of the new family will be the key to moving to green data centers,where service providers move to 40 and 100 Gbits/sec on a single blade by clustering as many 10-Gbit/sec ports as possible.

But will the insatiable demand for larger and more power-miserly data centers help accelerate the move to on-chip 10-Gbit transceivers? Przybus said that it’s obvious that FPGA designers will take a little time becoming familiar with multiple 10G transceivers on-chip. The slow adoption of discrete 10-Gbit transceivers as compared to 1-Gbit and 100-Mbit in past years indicates that the HXT FPGA will not be the market leader in the Virtex-6 family overnight. Nevertheless, Przybus predicted pent-up demand for the FPGA from the server and enterprise switch community, with optical transport applications following.

Altera Corp. certainly sees the high-end transceiver as an important differentiator. On the same day (Feb. 2) that Xilinx launched the Virtex-6 and Spartan-6, Altera announced an FPGA with 11.3-Gbit/sec transceivers, the Stratix IV GT. Altera is splitting the difference between speed and port count, with a maximum of 24 11-Gbit transceivers on one GT device, along with another 24 rated at 6.5 Gbits/sec. For more cost-sensitive WiMax and Passive Optical Network infrastructure equipment, Altera is adding 3.75-Gbit transceivers to the Arria II GX family.

Given the fact that telecom and data communications no longer dominate FPGA applications as they did at the end of the 1990s, it may seem odd that the industry’s two leaders are stressing feature sets for this market, when they are also plumbing new opportunities in automotive and factory-floor designs.

At Xilinx’s anniversary, Infonetics Research President Michael Howard and BDTi President and founder Jeff Bier traded ideas on the drivers for FPGAs in communication infrastructure. Howard said that, regardless of the recession, 40-Gbit data centers were here today, and 100-Gbit centers would follow in the 2013-15 time frame. This requires aggregated 10-Gbit channels as fast as designers can support the end equipment, which might mean good news for FPGAs with plenty of on-chip 10-Gbit transceivers.

Both Bier and Howard support the idea that continued wireless backbone expansion could help bring technology markets out of the recession. Howard said that WiMax may still be referred to as “4G” in some circles, but the mainstream operators will depend on Long-Term Evolution for their next generation of base station. And the LTE networks being planned require flexibility in implementation.

What does this imply for baseband algorithms? Bier said that cost/performance ratios favor FPGAs over traditional DSP processors. If better DSP blocks for advanced turbo coding and modulation techniques become available, FPGAs could take the lead in 4G base stations.

Of course, the system-level design assistance required in these markets plays well with the Targeted Design Platform announced by Xilinx along with Virtex-6/Spartan-6. Later this week, I’ll take a look at how this platform may accelerate application development.