Lattice sticks with open RISC

Most of the attention in the release on Lattice Semiconductor’s Version 8.0 of ispLEVER was on the software’s expansion of DDR support – all well and good, mind you, given the expansion of DDR2 in the embedded space. But I was more interested in the expansion of the RISC Lattice Mico32 development system. The environment now includes a newer version of a GNU compiler, and a triple-speed MAC IP core.  Lattice also announced it would be working with Beyond Semiconductor on compiler tools for Mico32.

There are wags out there who will say that “Those who can, brand their RISC, those who can’t, go open source.” The hot competition in recent weeks between Xilinx with ARM and Altera with MIPS would seem to lend credence to that view. I’m grateful to Kevin Morris at FPGA and Structured ASIC Journal for poking a hole in that particular hype balloon, in an essay at the end of October. Morris gave us a history of RISC-hype in FPGA realms, and suggested there are fewer customers who are disposed to use fully-characterized RISC cores than one would guess.

I see Lattice Mico32 as more equivalent to the MicroBlaze – a quick-turning 32-bit soft alternative to smaller logic or signal-processing blocks. There is a development learning curve, but much less than with an ARM or RISC instruction set. This is not to say that five years from now, most FPGAs with significant integer processing power will be based on an ARM or MIPS core. But for the time being, Lattice is right to promote generic, open-source RISC. It may prove just as valuable as all these fancy-shmancy name brands.