A new tack for DAC

Questions on the continuing relevance of the Design Automation Conference have been prevalent since mid-decade at least, as the EDA industry reaches both maturation and saturation points, particularly for standard-interface boards and systems. Seems like the FPGA industry is one of the few spots where real innovation is being demonstrated at next week’s DAC in San Francisco, which begs the question of whether DAC can be propped up solely on the strength of FPGA-based tools. Here are three bright points at DAC for the FPGA specialist:

• Aldec Inc. is claiming that its new mixed-language Register-Transfer Level (RTL) simulator, Active-HDL Designer Edition, will offer better support for a mix of Verilog, VHDL, and SystemVerilog in a single design, than those supplied from FPGA vendors themselves. Sounds like Aldec is giving a direct challenge to FPGA players with internal suites. By the way, the Aldec package is $1,995.
• Real Intent Inc. will show Ascent Path-Based Verification tools that are robust for functional verification in explicit-X and implicit-X assignments in FPGA design, corresponding to RTL X assignments and non-resettable flops, respectively. Ascent was first discussed several months ago, but the DAC demo will show fully automated capabilities in handling X assignments.
• GateRocket Inc. has expanded its RocketDrive product line to cover the Stratix IV FPGAs from Altera Corp. GateDrive is an FPGA-based hardware tool that accelerates HDL simulations. The drives now cover all major Xilinx and Altera architectures. GateRocket also will be showing Version 4.0 of its RocketVision debugging software.

Keep your eyes open for more DAC launches in the FPGA space, and let me know about anything that is worth crowing about.