Size as its own virtue

It’s funny how this blog downplayed the virtues of bigger and faster, only months before the Aug. 29 Economist declared in no uncertain terms that “Big is Back.” In celebration of such sentiment, Altera Corp. launched on Sept. 14 what it called “biggest FPGA yet,” Stratix-IV E, which scales to 820,000 logic elements (at this point, it’s almost irrelevant to talk about equivalent gates).

Four or five years ago, when gate array vendors saw FPGA developers eat into the mid-range of their product offerings, they suddenly forgot all the battles they had engaged in for 20 years on “equivalent gates,” and insisted that FPGA size simply didn’t count because gates did not equal gates. Utility of library elements was more optimized in a semicustom architecture than an FPGA, they said.

Umm, wrong. The ability of FPGA vendors to interface IP cores more efficiently, to make DSP and mixed-signal blocks more configurable, and to give users a choice of soft or hard processor cores for control-plane duties, has made the “system on a chip” slogan true enough to eliminate the semicustom competition on several vertical application fronts. The trick for the Xilinx-Altera-Actel-Lattice gang these days is to increase optimization of design tools at the same pace they increase FPGA size and accelerate internal speeds and I/O transceivers. So far, they’ve been doing pretty well on that front.

I suppose we can expect renewed races among the main FPGA players this fall over who’s on first in speed and size. That’s of secondary interest. What’s more interesting is that FPGAs have become sophisticated enough to integrate a core processor and primary peripherals in almost any realm where an integer MPU, DSP, or microcontroller once held sway. That’s why we see moves on the MCU front like today’s PSoC intro from Cypress.

Altera has grabbed a fleeting award with Stratix-IV E, but it’s more relevant that all four major FPGA players are doing so well on function integration at the high end. This caucus race is over, and all shall have prizes. Except maybe the remaining gate array vendors.