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Embedded in fiber

June 16, 2009

The growing trend among fiber IC specialists like Zarlink Semiconductor Inc. and Luxtera Inc. to bundle fiber optic cable, SFP+ transceivers, and photonic interface ICs in a single package for “active optical cabling” has spurred a similar trend among mezzanine card fans. Take a Xilinx Inc. Virtex-5 FPGA, bundle it with multiple channels of fiber interfaces, and embed the resulting transceiver in an XMC/AMC formatCurtiss-Wright Controls Embedded Computing is calling this a rugged transceiver module, but I call it a pretty useful way to handle multiple protocols in a small transceiver.

The common approach in the XMC card and the AOC subsystem is that the protocol controllers for E/O conversion and packet handling are placed very close to the E/O interface. While this would seem to make a lot of sense, FPGAs or network processors for packet processing traditionally have been placed on the line card. This could be the first step in making the line card itself a mezzanine-card format. The interesting trend to observe in the next year or two is how higher-layer protocol processing is partitioned: will all Ethernet MACs or Fibre Channel controllers turn into cores in the FPGA? Will they remain discrete devices, but be placed in the AMC module?

Ultimately, this may have an impact on what is known in desktop realms as the LAN-on-Motherboard (LOM)market. Maybe the networking MAC won’t be next to the primary system processor after all. Maybe it will be embedded in a transceiver module in daughter-card or AMC format. Or maybe it will be embedded in an integrated SFP+ and piece of cable. In any event, an FPGA is likely to be front and center in future designs.

 

Posted by Loring Wirbel on June 16, 2009 | Comments (3)

April 16, 2010
In response to: Embedded in fiber
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June 17, 2009
In response to: Embedded in fiber
pietro commented:

how will you handle the interconnection and algnement of an optical fiber in the fpga case ? any easier way enisageble wrt today problems ?


June 16, 2009
In response to: Embedded in fiber
Andy T commented:

SFP+ was all about simplification of the optical module, boiling it own pretty much to the PMA and not much more. Ali Ghiasi and I were among the first proponents that fought in standards committee for this simplification in OIF, in the days when 300 pin MSAs were just getting the nod of the standards body's approval. The SFP+ gave system designers the lowest power, small form factor, configurable/provisionable PHY performance levels, and, for the most part, a protocol agnostic interface. Are you now suggesting, Loring, that we'll see system architects extrapolate optical modules/active-cables architectures to housing a 30Watt 2,000k Veratix 7 GX in future (Xilinx and Altera will probably merge, having depleted all their cash in the litho wars of the 201x's), given protocols and embedded payloads are getting a lot more complex than the 1 start and two stop bits of old, and then will we see a 2000 pin MSA being pushed to commodity status by Ciscatel (another consolidation)? If the goal of complete, flexible, alterable, SoC is to be achieved, how does pushing protocol handling, a miniscule portion of the die size of upcoming 22nm FPGAs, allow the flexibility needed for inventory consolidation and protocol flexibility for box-building OEMs? One interface that does everything, including boiling a nice hot cup of tea.

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