FPGAs vs. ASICs/ASSPs in the digital down-converter

Two authors from Pentek Inc. have just posted a fascinating study on digital down-conversion (DDC) at Embedded.com. While one hesitates to call any conclusion a slam-dunk, the case for using FPGAs rather than signal-oriented ASSPs in software-defined radio (SDR) is a strong one.

Pentek offers a range of DDC radio modules, in the 714x/715x series, that convert specific high-frequency signals to baseband. Most are based on Virtex-4 or Virtex-5 architectures from Xilinx Inc. The authors include a case utilizing a dedicated DDC from Texas Instruments Inc., the TI GC4016. If I can quibble with semantics, I would not join the authors in calling this an ASIC solution, but would refer to it as an ASSP. I’m still one of those traditionalists who think that a signals-centric ASIC should be an array- or cell-oriented programmable block with special IP for MACs, FIR filters, etc.

But I digress. The conclusion of the authors is that efficient cores for implementing DSP functions are commonplace in FPGA architectures today, and they have all but eliminated the case for using an ASSP or ASIC. The authors show the range of functions carried out in different members of the 714x/715x family, and say that a common FPGA architecture can be used for all the modules. They conclude that “this is one of the fundamental concepts of SDR, and it’s difficult – if not impossible – to achieve with ASIC-based solutions.” They mention specific Pentagon SDR programs such as Joint Tactical Radio System as being optimal for IP-based FPGA architectures.

There are caveats attached, as the authors point out that FPGAs are best with high channel densities and narrow bandwidths. If the radio only uses a handful of channels and bandwidths are 100 MHz or greater, a dedicated ASSP may be more cost-effective. But I’m not surprised to see FPGAs come out the winner in the majority of SDR cases.