Can FPGAs help speed the ASIC design cycle?

Something tells me that Kawasaki Microelectronics America Inc. may be more straightforward than other ASIC vendors in confronting FPGAs’ threats to ASICs. K-Micro has gone public with an effort to use FPGA-based boards in its CatsEye development system to help speed development of complex ASIC designs.

Yes, you heard right. K-Micro is offering boards that combine the Xilinx Virtex-4 with the K-Micro PCI Express physical-layer core. By modeling ASIC designs in FPGAs in early stages, the designer can raise the chance of first-pass success in the final ASIC. Of course, there’s always the chance that the Virtex customer will find the FPGA architecture preferable to the next step of ASIC implementation, but K-Micro is betting that most users of CatsEye will continue to see an advantage in footprint and cost for ASIC conversion.

K-Micro’s CatsEye is not just a massive sea of gates, but a complex core-based ASIC with two MIPS32 24Kf cores and two Gigabit Ethernet MACs. There is no doubt an element of risk and a certain sense of “If you can’t beat them, join them,” in offering an ASIC development environment based on FPGAs. But I have to hand it to K-Micro for not hiding their collective heads in the sand on the role of FPGAs in displacing ASICs.