Driver Assistance: Algorithms are key
The initial video at FPGA Gurus and the follow-on, soon to be posted, both focus on automotive applications. Buyer recession or no, both Xilinx Inc. and Altera Corp. see in-vehicle information systems and camera aggregation as being significant vertical applications to test the limits of FPGA processing power.
This week, Nikkei Electronics Asia’s Tech-On! published a nice piece from Altera on development of lane-departure warning applications. I was less interested in the use of Nios II cores within a Stratix topology than I was with the involvement of third-party software vendors in optimizing algorithms for an FPGA. In this case, the company responsible is Elektrobit Automotive GmbH.
The lane-departure software from Elektrobit, the author stresses, is a floating-point C-based source code that was not originally developed for embedded applications. It is based on the PreVENT SAFELANE European project. Altera marries this with the Stratix II-based Platform ASSP Replacement Infotainment System, or PARIS-1.
The latter half of the article discusses how code can be optimized with the SOPC (System on Programmable Chip) Builder, particularly in the streaming subsystem that must provide near-real-time information to the driver information processing system.
In recent years, FPGA vendors have emphasized competitive differentiators in both speeds and feeds of the hardware, and in the variety of IP cores available. The Elektrobit involvement may show another interesting competitive realm for future applications, both in automotive and other verticals. Choosing the ideal software algorithms, and optimizing them for a particular architecture, may represent the liveliest FPGA playing field in the next decade.
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