11G transceivers get real

When Xilinx first introduced its Virtex-6 FPGA family early in 2009, the company hinted at its high-end HXT FPGAs with GTH transceiver blocks, though designs with the fastest blocks did not begin in the first half of the calendar year. This week, the blocks are elements in ISE Design Suite 11.3, and Xilinx is ready to initiate designs with 10-Gbit interfaces.

It is no accident that the blocks are rated at 11 Gbits/sec, to handle the overhead and error-correction of 10-Gbit interfaces. Xilinx also offers hard IP for Ethernet MACs and PCI Express interfaces. Xilinx is keeping an eye on higher-speed InfiniBand and Fibre Channel options as well, to see if additional IP cores make sense for the HXT FPGAs.

The highest-end member of the HXT family has 567,000 logic blocks, and can incorporate up to 72 transceivers with an aggregate speed of 580 Gbits/sec. Only 24 of these can be the 11-Gbit GTH transceivers, though they can be placed on an FPGA along with up to 48 6.5-Gbit GTX transceivers. The sheer number of transceiver blocks rival those of high-end Ethernet switches or network processors on the market.

ISE Design Suite 11 includes two high-level tools to aid in such integrated serial design. The Transceiver Wizard allows designers to use high-level commands and a graphic user interface to configure transceiver parameters. The ChipScope Pro Serial IO toolkit allows real-time debugging using such tools as bit error-rate testing.

Let’s face it, it’s taken a long time in the networking industry at large for 10-Gbit ports to replace their 1-Gbit predecessors. There are 40- and 100-Gbit Ethernet prototypes waiting in the wings, so Xilinx is bringing its 11-Gbit transceivers to market just in time for the post-recession design rush.