Crack that crypto!
Pico Computing Inc. has been showing up a lot on this blog lately, in contexts as varied as gene sequencing and financial analysis, but we would be remiss not to mention the company’s announcement Jan. 29 of the use of its FPGA cluster to crack 56-bit Data Encryption Standard, testing more than 280 billion keys a second. The demonstration uses 176 Xilinx Virtex-6 devices on 11 EX-Series PCI Express boards.
As the company stresses in its press release, DES has largely given way to Triple-DES or Advanced Encryption Standard, but is still used in many mainstream security applications. What is important to recognize for this readership is that parallel FPGAs are taking over many crypto duties from DSPs and ASSPs, and that brute force attacks on any kind of crypto system – AES, public-key, etc.- may become feasible as key-testing systems become larger and more parallel, even as they stay within a standard rack-mounted platform. This Pico project was implemented in a 4U design.
Pico is showing this DES cracker at the Black Hat DC 2010 conference in early February.
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