Gigabit to the Masses

Consider this a sequel of sorts to the last post on Virtex and HyperTransport. When Altera Corp. launched its Arria II GX development system July 27, one aspect of the introduction failed to gain much comment or attention, perhaps because it’s considered commonplace. These days, transceivers on mid-range FPGAs are assumed to support multi-gigabit-per-second speeds, and the battle for high-speed backplanes is no longer relegated to Virtex vs. Stratix. The Arria platform was specifically intended to meet PCI Express 2.0 specs.

Did I hear someone say “So what?” If you’re designing virtually any IT or embedded industrial system where PCIe plays a role, it should matter very much. MAC and physical-layer characteristics of a vendor’s transceivers will play an increasingly important role in all systems currently entering design, including those for which entry-level FPGAs are still being considered. Yes, there are plenty of designs out there still based on CAN or 10/100 Ethernet, and transceivers supporting 3.75-Gbit speeds may seem like overhill.

But within the next year or two, 1-Gbit speeds will be accepted as table stakes for virtually any design in any field. FPGA vendors are wise to bring support for higher speeds down to every product class. Meanwhile, the Virtex-Stratix war can move to 10 Gbits/sec, as OEMs assure me the long-awaited commoditization of 10-Gbit Ethernet is within 18 months of realization. Hey, wait, didn’t they say that five years ago?