DAC treats, part 2

I had to guess that more FPGA-related DAC suggestions would pour in, and that the omniscient Nanette Collins would have a great suggestion – albeit not wearing her DAC publicity hat, that wouldn’t be prudent. Nanette also works directly with EVE-USA Inc., co-verification specialist, and pointed me to the company’s ZeBu Server, a billion-gate emulator based on the Xilinx Virtex-5 LX330. The emulation system is configured in two-slot and five-slot chassis versions.

We’ve talked before about how emulation systems covering multiple ASICs have shrunk from room-size to desktop, or in some cases to PC add-in cards. The EVE ZeBu is not intended for simple single-FPGA emulation, but for multiple FPGA-ASIC-ASSP system-level hardware verification, with a range of 10 million to 1 billion gates. The emulator can accommodate up to 25 users, support design clocks to 30 MHz, and support up to 100 Gbytes of DDR2 memory. Connections to a host PC are through PCI Express, allowing for high-bandwidth test capability. Not only does EVE offer its own zFast ZeBu RTL synthesis, but the internal automated compiler does not change the RTL setup from FPGA synthesis, allowing for a very rapid emulation setup procedure.

I should also mention that the latest Xcell Journal from Xilinx gives a little history on ZeBu development, proving I should keep up to date with the journal before closing off the pre-DAC entrants. OK, we still have a few more days before the opening bell, any other FPGA goodies I may have missed?