FPGA as a test-drive template - and hedge

The use of FPGAs as evaluation tools for fabless semiconductor companies is growing daily, and over the Memorial Day weekend, the New Electronics web site in England featured a new wrinkle on this effort. Galazar Networks Inc. elected to use Virtex FPGAs as emulation vehicles for the MXP2 multiplexer/mapper chip, prior to that chip’s tapeout.

The announced reasoning was to allow the OEM to carefully consider alternative I/O and processing options to optimize Sonet mapping options into OTN channels. But given that the OEM in this case was Nortel Networks Inc., currently in bankruptcy, one can also conclude that the use of an FPGA emulator offers a hedge of sorts: if the primary customer either goes out of business or radically changes business plans, has the ASSP vendor defined the target chip in such a way that other customers can be found?

The article also mentions using the evaluation module, which incorporates three separate Xilinx FPGAs, to test clock recovery and error-correction block functionality. If this was the primary reason the FPGAs were being used, I might suggest turning to a dedicated verfication accelerator, like the GateRocket RocketDrive, rather than develop a dedicated emulator. But Galazar made clear that its primary goal in implementing MXP2 in FPGAs was making sure it got the feature set the customer wanted.

The ASSP company of the 21^st century may well want to consider utilizing FPGAs as a hedge as the market recovers from the 2009 recession. Consolidation among data communication and telecom OEMs is likely to continue, and ASSP companies will be severely resource-constrained, occasionally preventing them from doing second spins of a design. Making sure a design is optimal before tapeout could be the ultimate insurance policy in hard times.