Picking your packet tasks

Siverge Networks Inc. has given us a nice one-to-one comparison of how traditional ASICs and FPGAs can be combined for networking processing tasks. Details on the specific FPGA architecture used in the new Griffin chip set are scant, because Siverge is a fabless ASSP company, not an OEM. Nevertheless, the launch of its new SivGate/Griffin universal gateway chips points out how a variety of programmable architectures can coexist in one chip set.

What the company has publicly revealed is that the ASIC was used for well-defined networking protocols at Layers 1 and 2, the physical and data-link layers, respectively. These protocols are well-characterized in realms such as Sonet and Ethernet, as well as standard digital hierarchies. At the same time, Siverge can preserve programmability for per-channel services.

The FPGA is used for circuit emulation, Metro Ethernet Forum services such as pseudowire, and packet analysis at higher network layers. One can make the argument that some of these functions are almost ready for an ASIC or a hard-wired ASSP, but Siverge has performed some intelligent partitioning between ASIC and FPGA – at least for now.

One would hope that there is enough of a telecom OEM market left these days for Siverge and other players to continue to upgrade network-edge chip sets. By that time, there may be enough lower-cost FPGA options to even consider an FPGA as a high-volume, low-cost alternative for Layers 1 and 2. For now, Griffin stands as a good example of where ASIC/FPGA/ASSP partitioning is headed.