Virtex, Spartan snare dual crypto design win

Xilinx’s Virtex-5 and Spartan-3 have both been chosen in a reference design for a cryptographic module. Japan’s National Institute of Advanced Industrial Science and Technology (AIST) will use the two FPGA architectures in the SASEBO-GII board, which the government agency will promote for cryptographic testing, according to Xilinx’s Japan subsidiary Xilinx KK.

In some senses, the design was no surprise, since SASEBO-G was based on the Virtex-II. But since the second generation reference design was developed around the demanding FIPS 140-2 standard, this indicates the growing role of FPGAs in mainstream cryptography. Here in the U.S., we’ve seen the DSP blocks in Spartan-3A DSP used in conjunction with standard mezzanine card architectures like VITA 57 FMC, to displace standalone DSP processors in several high-security designs.

SASEBO-GII, the third such generation to use Xilinx FPGAs, utilizes Virtex-5 LX30 and LX50 devices for primary crypto processing, while the Spartan-3A is used as an interface circuit for partial reconfiguration by the user, and for side-channel attack evaluation. Tokyo Electron Devices Ltd. will offer commercial versions of the board.