Xilinx adds FMC arrow to its Targeted Design quiver

You’ll probably be seeing news this week on the extension of the ISE Design Suite from Xilinx Inc to Version 11.2, supporting the Virtex-6 and Spartan-6 families. That’s all well and good, but we would not want to overlook the fact that the new FPGA Evaluation Kits simultaneously released this week support the latest American National Standards Institute standard developed within VITA, the FPGA Mezzanine Card, or VITA 57.1. The use of a mezzanine card that follows in the footsteps of PMC and XMC fits with Xilinx’s earlier announced strategies of domain-specific platform kits, since it makes it easier for board-level developers to port applications in areas such as DSP and networking.

I would no more claim that the vote of confidence in FMC by a major FPGA player would flip the VITA world rapidly to use of FPGAs, than I would claim the arrival of the Advanced Mezzanine Card in the PICMG world would make ATCA/MicroTCA take off. Every board-level standard must be developed with time and proof of principle, as we have seen in VME, PCI Express, and Compact PCI worlds.

But what seems obvious is that the multiplicity of mezzanine card standards makes the daughter card more palatable in applications where real-estate allocation is critical. Combine the ISE 11.2 Design Suite, the expanded IP portfolio, the highly-defined evaluation kits for Virtex-6 and Spartan-6, and displacement of DSPs and network processors becomes painless. The results could be radical for Xilinx, for its partners, for VITA supporters, and for developers of system boards across communication, imaging, mil-aero, and embedded-control worlds.