Software development flows

I recently participated in the IP-ESC 2009 conference in Grenoble, France. This event, which brings together many of the leading IP vendors and their customers - SoC designers - focused on some of the key trends in SoC design, including growing complexity, increased programmability, and the need for robust development environments.

A clear trend that has been emerging over the last few years is the growing complexity of SoCs. The two aspects driving this are 1) the continued industry move towards total system integration; and 2) the dramatically increased performance requirements of these chips. From an integration aspect, modern SoCs need to support a large number of technologies on a single chip including, for example, communications, multimedia, GPS, connectivity, and storage. The systems architecture required to achieve this level of integration is hugely complex. From a performance aspect, the advancements in technology, particularly in wireless baseband and multimedia have pushed the boundaries of modern SoC design.

Looking at wireless baseband, in a relatively short period of time, the mobile handset has evolved from a voice-centric device to a data-centric one, particularly since the introduction of 3G, 3.5G and now 4G wireless standards. The increase in complexity is dramatic: for instance, early data services wireless baseband protocols supported up to a 1Mbps; now, with the emergence of LTE, up to 150Mbps needs to be supported on the receiver channel alone. Add to this the requirement to support all existing wireless standards, including 2G- GSM, GPRS, EDGE; 3G- WCDMA, HSPA, TD-SCDMA; 4G- LTE, and one quickly understands that traditional processor architectures featuring dedicated logic for each standard are virtually unfeasible in terms of both cost and power consumption. This leads to an advanced practice, becoming more and more common these days, called SDR (Software Defined Radio). In this approach, a single programmable architecture supports multiple air interfaces using different software components.

From a multimedia aspect, the evolution towards feature-rich multimedia products supporting High Definition video and audio have driven SoC and processor design to new levels of complexity in order to meet the performance demands. And similar to wireless baseband design, these modern multimedia processors need to support an increasingly large number of video and audio standards. For this new generation multi-standard solutions, placing dedicated logic for each standard is impractical. A programmable multimedia architecture however can support all the standards in software, sparing the need for a dedicated logic for each standard.

“It’s the Software, Stupid”

As discussed above, in most modern SoCs, an increasingly large number of technologies need to be integrated into a single chip, many with more than one standard that need to be supported. As a result, the functionality of the SoC continues to migrate from hardware implementation to embedded software. This trend is evident in the increased design effort and cost that goes into SoC development. Today, embedded software development poses the greatest challenge in the SoC development cycle and based on latest statistics, software development cost represents 80% and more of the total SoC development cost (source: International Technology Roadmap for Semiconductors, 2008).

To meet the demands discussed above, engineers are increasingly using programmable architectures in SoC design. As the SoC need to support very demanding use cases, the programmable architectures are becoming very sophisticated in order to meet these requirements with minimal power consumption and cost. These state-of-the-art processors are very different from the standard DSPs or CPUs used in the past.

As an example, the CEVA-XC is an advanced DSP processor supporting up to 64 MAC (multiply-accumulate, a very common DSP operation) operations in a single cycle. These types of processor can deliver 32 to 64 times the computational performance of the single or dual operations DSP cores from only a decade ago. We can find similar cases with other modern processors which are based on VLIW (Very Long Instruction Word) SIMD (Same Instruction Multiple Data) or Vector architectures.

These modern processors are too parallel and complex to be programmed in assembly language. This leads to a need to program them in high level language such as C. Programming the architecture in C level significantly simplifies the software development effort by hiding the architecture complexity from the software programmer and by reusing a lot of standard C code.

Nevertheless, the main challenge is in meeting the target performance while meeting time-to-market constraints. A standard C compiler is no longer sufficient; instead, advanced compiler capabilities as well as a comprehensive optimization environment is essential in order to make C-level programming possible for demanding use cases. This environment should enable achieving the best possible performance in C level and facilitate software optimization process in C, eliminating the need to do further optimization in assembly.

Such a development environment should offer C-level optimization specially targeting the software optimization process, including: automatic optimization tools such as build optimization and strong compiler, application profiler, cycle-accurate system-aware simulation support, set of optimized algorithmic libraries and more.

Check out a video example of the CEVA C-level optimization tool chain.

Eyal Bergman, Director of Product Marketing, CEVA