Welcome to the past: Architecture strategies resume precedence as interconnect capacitance limits performance

We stand on the brink of a fundamental discontinuity in silicon process-technology unlike anything most of us have seen. For almost two decades, a period of time spanning many of our entire education and careers, we have been beneficiaries of a silicon process-technology that would let us build almost anything we could imagine. Now, all of that is about to change.

For the past five years, capacitive loading of interconnect has grown to be a significant factor in logic speed and has limited the scaling of integrated-circuit performance. To compound the problem, recently, interconnect resistance has also started to limit circuit speed. As we transition from 90 nm to 32 nm, by the year 2010, copper sheet-resistance (mÙ per sq) will increase by almost a factor of five. These factors can render obsolete current designs and current thinking as interconnect-dominated designs and architectures become unable to meet the requirements of the market place. Given these fundamental interconnect challenges, we must look in new directions and turn to architecture, logic design and programming solutions to these challenges.

We must develop architectural solutions that will deliver compelling performance improvements with the assumption of little to no improvement in average interconnect capacitance, resistance, and electromigration. Architecture strategies for dealing with interconnect must be synergistic with low-power and aggressive energy efficient requirements. In addition, they must be cost efficient.

Possible future solutions must focus on improvements at the datapath, processor, memory and system levels of the interconnect hierarchy. Programming and logic approaches must be developed that will support higher application specific performance in spite of interconnect trends.

Importantly, the term "interconnect" is not solely about the impact of resistance and capacitance on the metal system in an integrated circuit. At the system level, especially, this term should also comprehend communication protocols and their implementation.

Also, it is important to realize that a future architecture solution to interconnect challenges may actually be found in older products and ideas that dealt with interconnect issues at the board and backplane. We may find much inspiration by considering the work done in creating early computer architectures – which, by the way, were often targeted at DSP types of tasks. These systems were often forced to minimize interconnect and to expose and deal with interconnect due to the limitations of what was integrated in monolithic components of the time and the subsequent strengths and weaknesses of integrating a system at the board and backplane level.

The seriousness of this situation cannot be overstated. If you are involved in DSP, processor or chip system-architecture, logic design, programming tools, or applications that are impacted by interconnect, then these topics should be of interest to you. In future posts we will begin to peel the onion to better understand the impact of process technology on our future direction on not just architectures, but also on our industry.

—Ray Simar, Texas Instruments