Price for a new SATA I/O $700M. A complete AMS verification? Priceless!
The big news of the morning was that Intel has discovered a “design error” in a 65nm support chip for their new Sandy Bridge based systems, affecting the SATA disk-drive I/O controller.
“The chipset is utilized in PCs with Intel’s latest Second Generation Intel Core processors, code-named Sandy Bridge. Intel has stopped shipment of the affected support chip from its factories.”
Apparently the problem is not “functional“, and is due to “degradation” of performance that was discovered post-silicon during the company’s “ongoing QA“. In their update conference call, Intel said the root cause was due to “a design oversight“, and could be fixed in one of the “later layers of metal“.
This news broke just as I was rushing to meet a deadline for my upcoming article on IC simulation and verification. As they say, timing is everything! If ever there was a great lead-in for an article on the challenges of design verification, this is it. It almost writes itself (well almost… in my dreams)!
The impact is staggering in dollar terms, even if you are a $40B+ company.
“Total cost to repair and replace affected materials and systems in the market is estimated to be $700 million.“
And I used to lose sleep before a tapeout that had tens of thousands of dollars at risk!
Credit goes to Intel for the prompt disclosure and explanation. We can infer a few things from the information provided.
- Degradation over time can be associated with NBTI (negative-bias temperature instability) or HCI (hot-carrier injection). Intel has published reports on these phenomena in their Journal.
- It is very difficult to model and simulate these aging effects, and a 65nm chip may have been thought to be immune.
- Improper biasing, or mismatching of a higher voltage domain to a lower voltage device can contribute to such problems.
- Since the device was still functional, but degraded over time (as much as 3 years according to Intel), my guess is that the metal fix is to correct a supply rail or bulk connection error.
There are many lessons here… big ones!
- First, functional verification is not sufficient to ensure a successful tapeout, even if you can get to 100% coverage.
- Analog verification is just as important, maybe more important than digital functional verification
- Sometimes it’s the little things that bite you.
- Reliability simulation is a largely overlooked area of design verification.
I will cover many of these topics in my March 17th EDN cover story on IC Simulation.
In the meantime, here is my new version of the KISS strategy:
It’s not all about functional verification. RTL is not real.
Know it’s the silicon…
Kev (simguru) commented:
When I worked on Verilog-AMS back in the 90’s my goal was to enable Verification of “Large D, small A” SoC & systems - the kind of thing that would make it easier to catch these bugs. Unfortunately Cadence screwed up the standard and failed to provide a back-anotation scheme (analog equivalent of SDF), so it never got into use in digital design flows as intended.
I’d like to say “I told you so” to someone, but who?
Mark commented:
But surely if it was any of the reliability issues suggested above then it would have shown up as a major failure during reliability and lifetime qual testing that should precede a production release.
Mike Demler commented:
Thanks for all the comments!
>Paul - apparently not EM, since that is pretty binary from a functional point of view, not statistical.
>Coby - I am not familiar with Micrologic, but I am interested to learn more.
>Apurva - yes, that is one of the original aging simulator implementations, from Celestry.
>Gus - I really don't think you want an unpredictable SATA I/O.
>Alex - I am also not familiar with Invarian, but interested to learn more.
>Brad - One problem has been foundries not including aging models in their PDKs, so "market" has been small. I got push back when I predicted the market opportunity for aging simulators while I was in EDA, so vendors have not emphasized these tools.
Paul Rako commented:
Could it be an electromigration problem leading to whiskers and metalization shorts?
Coby Hanoch commented:
Micrologic’s nanoRV is an interactive reliability checker. It was just recommended by STARC (Japanese Semiconductor consortium) as part of their recommended back-end flow.
Apurva Soni commented:
Relxpert from Cadence is one of the reliability simulation tool.
Gus in Denver 99gus commented:
I will take all of the Intel chips that “will only last 3 years ” I promise to mark them with an expiration date. ( Is that 3 years of operation or 3 years of shelf life )
Alex Samoylov commented:
Not a “market-leading” yet, but Invarian SoC/Analog solution with robust reliability verification built into the tool may be the answer to the problem.
Brad Pierce commented:
Mike, which are the market-leading “reliability simulation” tools?
