New multi-core embedded processors accelerate 4G LTE applications

The 2011 Mobile World Congress kicks off in Barcelona on Monday February 14th ( better known as Valentine’s Day in the florist trade), and if events leading up to it are any indication, you can expect a flood of announcements on new smartphones, tablets, mobile operating systems, and 4G LTE devices.

It’s going to be interesting to see what follows after these stories that we’ve covered in the last few days.

• High performance DSP IP cores are ready for LTE-Advanced
• Android gains on Symbian
• Verizon’s LTE: Cellular-Served Bits, Delivered Even More Speedily
• Nokia calls in Microsoft

To go with these announcements, on Monday, January 31, ARM announced the development of two new embedded real-time processors targeting LTE and LTE Advanced applications; the Cortex-R5 and the Cortex-R7. The new designs build upon the ARM Cortex-R4 processor, which was introduced in 2006, by maintaining binary compatibility.

The Cortex-R embedded real-time processors complement specialized DSP processors in 4G modem applications. Both the R5 and R7 can be employed in single or dual-core configurations. A dual-core configuration reduces software overhead by allowing simultaneous processing of the download and upload channels that are employed in an LTE paired-spectrum FDD (frequency division duplexing) wireless network architecture. ARM will be manufacturing the CPU IP cores in a low-power 28nm CMOS process.

The R5 adds to the features of the previous generation R4 by extending error management to the busses, so that reliability of transactions is increased.  You can configure the R5 during synthesis to optimize power efficiency. For example, designers can configure the R5 with various cache sizes, and you can choose to use single or double precision FPUs (floating-point units) with the licensed IP to save size. Other features of the R5 include a high priority Low-Latency Peripheral Port (LLPP) for fast peripheral reads and writes, and an Accelerator Coherency Port (ACP) providing cache coherency for increased data transfer efficiency and more reliable firmware.

The Cortex-R7 is said to provide up to a 70-80% uplift in performance, and adds SMP (symmetrical multiprocessing) with coherent caches between processors. The R7 supports full-fledged SMP without the need for an MMU (memory management unit), limited to 32b addressing of up to 4Gb of memory.

With the R7 you have the ability to extend error recovery to hard errors, such as stuck-at faults of up to 3-4 errors per memory bank, configurable through software for application-defined policies. Both the R5 and R7 support lockstep operation for backup of failure in in a single CPU.  The Cortex-R7 enables increased performance by allowing out-of-order instruction issue and completion. With the R7 register renaming feature you can maximize processing resources.  In a dual-core configuration, the Cortex-R7 provides the ability to maintain coherency between the data cache and main memory both for I/O and between processors.

Both the Cortex-R5 and Cortex-R7 processors are available for licensing today, and ARM has stated that four tier one licensees already have designs underway.  Further information is available at http://www.arm.com/products/processors/cortex-r