New Design Compiler Explorer promises faster digital implementation flows.

With Synopsys’ new DC (Design Compiler) Explorer tool, you can explore RTL early in the design phase, and perform what/if analyses to test various design configurations, without the need for a complete set of design data for your entire chip. The intent of the DC Explorer is to reduce the amount of time you would otherwise spend iterating in the full-blown Design Compiler, so that you can get to a good starting point for your synthesis flow in less time.

According to Gal Hasson, Senior Director of Marketing for RTL synthesis, power and test automation at Synopsys, DC Explorer has complete script compatibility with standard Design Compiler RTL Synthesis, and the tool will just ignore commands that don’t apply. Eyal Odiz, Vice President of Engineering for RTL synthesis, says that run times were 5-10X faster than DC Topographical in a set of example designs that ranged from 740K instances to 4M instances.

You can use DC Explorer to create a netlist for physical implementation and initial floor-planning, even if your RTL and constraints are incomplete. The Explorer will identify inconsistencies between the RTL and physical design, such as mismatched bus widths and infeasible timing paths.

Synopsys compared results from DC Explorer to DC Ultra RTL Synthesis, and found “10 percent timing and area correlation“, according to Odiz.  While I doubt that anyone would brag about 10% correlation, the company mistakenly used the term correlation when they actually mean mismatch (which would be [1 - correlation coefficient]).In other words, the results out of DC Explorer are pretty close to what you can expect to achieve with DC Ultra.

So, if DC Explorer is 5-10X faster, and produces results that match within 10%, just how much do you still need DC?  And why didn’t Synopsys just add this as a feature to DC, like a coarse/fine compiler option, rather than as a separate product? It would appear that Synopsys is risking cannibalization of DC in hopes of generating new product sales for DC Explorer.

This strategy is a result of the EDA business model.  While some of the largest customers will gain access to the new technology regardless, due to their right to “re-mix”, most customers on standard maintenance agreements will have no choice but to buy a new license. It will be interesting to track DC sales to see if there is negative correlation with DC Explorer. As Gal Hasson says, now most of the iterations in RTL design will be done in the Explorer, rather than in DC as it is done today. Eyal Odiz notes that high-end customers will not sacrifice the last 10% of performance or area. He recommends using the Explorer just to to clean up and explore RTL.  It is also worth noting that there are more physically-aware capabilities in DC, and that Explorer does not do all the same optimizations.