The Throttled World of Chip Design

I attended the EDA Consortium’s Annual CEO Forecast and Industry Vision shindig held at the Doubletree Hotel in San Jose last Thursday night. The CEOs on the panel included Mentor’s Wally Rhines –entertaining as always; Synopsys’ Aart de Geus—cool and scholarly as always; Lip-Bu Tan—Cadence’s relatively new CEO; and John Kibarian—founder and CEO of PDF Solutions and the new guy on the panel. To my mind, the panel was remarkably jovial and upbeat considering the recent tumultuous economic past of the electronics and semiconductor industry and considering that the EDA industry has just finished its second year of shrinkage. However, the forecast is for modest EDA industry growth in 2010, so everyone’s feeling somewhat better that the hemmorhaging seems to have stopped. You can read a more detailed account of the CEO presentations by industry blogger and commentator Sean Murphy here. His summary of the evening is “subdued”. I have a somewhat different take on the evening:

Is this what we’ve come to? Have we become essentially satisfied—even happy—with single-digit growth for one of the most innovative technologies if not the most innovative technology on the planet?

I don’t think so.

There was a huge elephant in the room and none of the CEOs pointed to it or cursed it in their avowed quest to get a bigger piece of the total semiconductor sales for their companies because EDA is “so essential” to semiconductor development. (That’s a dead horse they all continue to try to ride. Silicon is essential too. So are copper and aluminum. Should the costs of beach sand and base metals be tied to semiconductor sales too?). The elephant in the room is the staggering cost of developing nanometer chips. The press has done a mighty fine job of railing about multi-million-dollar mask costs over the past few years while essentially ignoring the skyrocketing cost of chip design and verification. Possibly because those costs are harder to point at. To my mind, you need not worry about a million dollars worth of mask costs (well OK, you can worry about those costs some) when you must first spend tens of millions of dollars to get the chip designed to the point where you can then generate those masks. Because of this huge design-cost increase coincident with the era of nanometer chips, only the highest-volume applications can make use of custom silicon. Everyone else makes do with ASSPs, microcontrollers, FPGAs, or some mix of standard parts. Therefore, everyone also makes do without the bulk of the EDA industry, thus restricting the market for the industry’s products. These costs have reversed the trend that popularized ASICs in the first place with the advent of gate arrays in the early 1980s.

What’s the reason for the huge increase in ASIC/SOC design costs? One word: complexity. Nanometer chips are immensely more complex to design. Each block inside of a nanometer chip is now as complex as an entire chip designed just a few years ago. Need a processor? Drop it into the chip and you’ve still got 99% of the chip left to fill. Need complex I/O blocks such as SATA, PCIe, or USB 3.0? Drop them in. Plenty of room left. As I’ve been writing for the past decade, SOC design today closely resembles board-level system design of the 1980s. The chip architect selects major blocks from an industry-wide catalog of designed, tested, proven components and then weaves them together with as little extra hardware as possible. Then the whole cake gets frosted with a thick layer of icing in the form of software, which breathes life into the SOC. So why is system design that’s based on SOCs so much more expensive than system design using standard parts and circuit boards? The answer to that question contains huge revenues and profits for the EDA company that successfully delivers the answer.

The huge elephant in that room at the Doubletree Hotel is squeezing out most of the world’s chip-design teams. Consequently, many fewer ICs are being designed. The costs and the risks are so immense that the potential return must be gargantuan. You’d better have a reasonable expectation of shipping many tens of millions of chips—even hundreds of millions—to recoup design costs and make a profit. There just aren’t that many end applications that can guarantee such volumes. And it all comes down to design costs.

So did we hear anything about this elephant in the room at the EDAC confab this week?

Nope. Wish we had.